Energy efficient scheduling for datapath synthesis

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 446-451

  Mohanty, Saraju P ^a   Ranganathan, N ^a  

^a University of South Florida   (United States)

Author keywords

Adders; Clocks; Energy consumption; Energy efficiency; Frequency; Minimization methods; Processor scheduling; Scheduling algorithm; Time factors; Voltage

Indexed keywords

ADDERS; ALGORITHMS; CLOCKS; DESIGN; ELECTRIC POTENTIAL; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENERGY CONSERVATION; ENERGY UTILIZATION; FLOW MEASUREMENT; HIGH LEVEL SYNTHESIS; SCHEDULING; SCHEDULING ALGORITHMS; SYSTEMS ANALYSIS;

CONSTRAINED ALGORITHMS; ENERGY-EFFICIENT SCHEDULING; FREQUENCY; MINIMIZATION METHODS; MULTIPLE SUPPLY VOLTAGES; PROCESSOR SCHEDULING; REDUCE ENERGY CONSUMPTION; TIME FACTORS;

ENERGY EFFICIENCY;

EID: 0038111483     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183175     Document Type: Conference Paper

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