Power: A first class design constraint for future architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1970, Issue , 2000, Pages 215-224

  Mudge, Trevor ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

ARCHITECTURAL DESIGN DECISIONS; DESIGN CONSTRAINTS; DESIGN CYCLE; EMBEDDED ENVIRONMENT; FUTURE ARCHITECTURES; HIGH PERFORMANCE COMPUTERS; PERFORMANCE IMPACT; POWER SAVINGS;

ECONOMIC AND SOCIAL EFFECTS;

EID: 84947570042     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44467-x_20     Document Type: Conference Paper

References (17)

1. D. Singh and V. Tiwari. Power Challenges in the internet World. Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design, Eds. T. Mudge, S. Manne, D. Grunwald, held in conjunction with MICRO 32, Haifa Israel, Nov. 1999, pp.8-15. (http://www.eecs.umich.edu/tnm/cool.html)
2. K. Wilcox and S. Manne. Alpha processors: A history of power issues and a look to the future. Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design, Eds. T. Mudge, S. Manne, D. Grunwald, held in conjunction with MICRO 32, Haifa, Israel, Nov. 1999, pp.16-37. (http://www.eecs.umich.edu/tnm/cool.html)
3. ChartWatch: Mobile Processors. Microprocessor Report, vol. 14, archive 3, Mar. 2000, p.43
4. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Jour. of Solid-State Circuits, Sep. 1996, pp. 1277-1284.
5. S. Furber, J. Garside, and S. Temple. Power Saving Features inAmulet2e. Power-Driven Microarchitecure Workshop, Eds. T. Mudge, S. Manne, D. Grunwald, held in conjunction with ISCA 98, Barcelona, Spain, June 1998 (http://www.cs.colorado.edu/grunwald/LowPowerWorkshop/agenda.html)
6. S. Moore, et al. Self Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. Int. Conf. on Computer Design, Austin, Texas, Sep. 2000
7. th Int. Symp. Computer Architecture, Barcelona, Spain, June 1998, pp. 132-141.
8. M. Johnson, M. Gupta and W. Mangione-Smith. Filtering memory references to increase energy efficiency. IEEE Trans. on Computers, vol. 49, no. 1, Jan. 2000, pp. 1-15.
9. th Int. Symp. Computer Architecture, Portland, Oregon, Dec. 1992, pp. 1-4.
10. L. Benini, et al. Address bus encoding techniques for system-level power optimization. Proc. 1998 Design Automation and Test in Europe (DATE '98), pp. 861-866.
11. th Int. Symp. on High-Performance Computer Architecture, Jan. 2000, pp. 218-227.
12. T. Pering, T. Burd, and R. Brodersen, Voltage scheduling in the lpARM microprocessor System, Proc. 2000 Int. Symp. on Low Power Electronics and Design, July 2000
13. G. Cai and C. Lim. Architectural level power/performance optimization and dynamic power estimation. Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design, Eds. T. Mudge, S. Manne, D. Grunwald, held in conjunction with MICRO 32, HaifaIsrael, Nov. 1999, pp.90-113. (http://www.eecs.umich.edu/tnm/cool.html)
14. th Int. Symp. Computer Architecture, Vancouver, Canada, pp. 83-94.
15. th Int. Symp. Computer Architecture, Vancouver, British Columbia, Canada, June 2000, pp. 95-106.
16. D. Burger and T. Austin. The SimpleScalar toolset, version 2.0. Tech Rept. Computer Science Dept., Univ. Wisconsin, June 1997 (see also http://www.simplescalar.org)
17. http://www.eecs.umich.edu/~tnm/power/power.html