A scalable ODC-based algorithm for RTL insertion of gated clocks

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 500-505

  Babighian, Pietro ^a   Benini, Luca ^b   Macii, Enrico ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK GATING; DYNAMIC POWER MANAGEMENT (DPM); GATED LOCKS; REGISTER TRANSFER LEVEL (RTL); COMMERCIAL TOOLS; GATED CLOCKS; HIGH SCALABILITIES; KEY FEATURE; LARGE CIRCUITS; QUALITY OF RESULTS; RTL DESIGNS;

AUTOMATION; BOOLEAN ALGEBRA; COMPUTER AIDED DESIGN; DIGITAL CIRCUITS; LOGIC GATES; QUALITY ASSURANCE; EXHIBITIONS; PRODUCT DESIGN; TOOLS;

ALGORITHMS; CLOCKS;

EID: 2942666728     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268895     Document Type: Conference Paper

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