Challenges in clockgating for a low power ASIC methodology

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 176-181

  Garrett, David ^a   Stan, Mircea ^a   Dean, Alvar ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; TIMING CIRCUITS;

LOW-POWER DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0033359348     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313913     Document Type: Article

References (13)