Impact of technology scaling in the clock system power

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 59-64

  Duarte, D ^a   Narayanan, V ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Capacitance; Clocks; Energy consumption; Flip flops; Integrated circuit modeling; Inverters; Microprocessors; Power generation; Power system modeling; Random access memory

Indexed keywords

BUDGET CONTROL; CAPACITANCE; ELECTRIC INVERTERS; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; POWER GENERATION; RANDOM ACCESS STORAGE;

CLOCK DISTRIBUTION; INTEGRATED CIRCUIT MODELING; INTER-WIRE CAPACITANCE; LEAKAGE POWER CONSUMPTION; POWER SYSTEM MODEL; RANDOM ACCESS MEMORY; RELATIVE IMPACT; TECHNOLOGY SCALING;

CLOCKS;

EID: 84948706668     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016875     Document Type: Conference Paper

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