-
2
-
-
0025594311
-
Buffer placement in distributed RC-tree networks for minimal elmore delay
-
L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal elmore delay", ISCAS 1990.
-
(1990)
ISCAS
-
-
Van Ginneken, L.P.P.P.1
-
3
-
-
0030697661
-
Wire segmenting for improved buffer insertion
-
C. J. Alpert, A. Devgan, "Wire segmenting for improved buffer insertion", DAC 1997.
-
(1997)
DAC
-
-
Alpert, C.J.1
Devgan, A.2
-
4
-
-
0031619501
-
Buffer insertion for noise and delay optimization
-
C. J. Alpert, A. Devgan, S. Quay, "Buffer insertion for noise and delay optimization", DAC 1998.
-
(1998)
DAC
-
-
Alpert, C.J.1
Devgan, A.2
Quay, S.3
-
5
-
-
0032652489
-
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
-
C. Chu, D. F. Wong, "A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing", IEEE Trans. on CAD, 18(6), 1999.
-
(1999)
IEEE Trans. on CAD
, vol.18
, Issue.6
-
-
Chu, C.1
Wong, D.F.2
-
6
-
-
0032685389
-
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
-
C.-P. Chen, C. Chu, D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation", IEEE Trans. on CAD, 18(7), 1999.
-
(1999)
IEEE Trans. on CAD
, vol.18
, Issue.7
-
-
Chen, C.-P.1
Chu, C.2
Wong, D.F.3
-
7
-
-
2342423095
-
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
-
J.-L. Tsai, T.-H. Chen, C.-P. Chen, "Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing", IEEE Trans. on CAD, 23(4), 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.4
-
-
Tsai, J.-L.1
Chen, T.-H.2
Chen, C.-P.3
-
8
-
-
0347761312
-
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
-
C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. Quay, "Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique", IEEE Trans. on CAD, 23(1), 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.1
-
-
Alpert, C.J.1
Chu, C.2
Gandham, G.3
Hrkic, M.4
Hu, J.5
Kashyap, C.6
Quay, S.7
-
9
-
-
0029716943
-
Simultaneous routing and buffer insertion for high performance interconnect
-
J. Lillis, C.-K. Cheng, T. Y. Lin, "Simultaneous routing and buffer insertion for high performance interconnect", GLSVLSI 1996.
-
(1996)
GLSVLSI
-
-
Lillis, J.1
Cheng, C.-K.2
Lin, T.Y.3
-
10
-
-
0034229328
-
Simultaneous routing and buffer insertion with restrictions on buffer locations
-
H. Zhou, D. F. Wong, I. Liu, A. Aziz,"Simultaneous routing and buffer insertion with restrictions on buffer locations", IEEE Trans. on CAD, 19(7), 2000.
-
(2000)
IEEE Trans. on CAD
, vol.19
, Issue.7
-
-
Zhou, H.1
Wong, D.F.2
Liu, I.3
Aziz, A.4
-
11
-
-
2442473117
-
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations
-
S. Dechu, Z. Shen, C. Chu, "An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations", ASP-DAC 2004.
-
(2004)
ASP-DAC
-
-
Dechu, S.1
Shen, Z.2
Chu, C.3
-
12
-
-
0348040111
-
Power-optimal simultaneous buffer insertion/sizing and wire sizing
-
R. Li, D. Zhou, J. Liu, X. Zeng, "Power-optimal simultaneous buffer insertion/sizing and wire sizing", ICCAD 2003.
-
(2003)
ICCAD
-
-
Li, R.1
Zhou, D.2
Liu, J.3
Zeng, X.4
-
14
-
-
0041633712
-
An O(nlogn) time algorithm for optimal buffer insertion
-
S. Weiping, L. Zhuo, "An O(nlogn) time algorithm for optimal buffer insertion", DAC 2003.
-
(2003)
DAC
-
-
Weiping, S.1
Zhuo, L.2
-
15
-
-
2342420999
-
Repeater scaling and its impact on CAD
-
P. Saxena, N. Menezes, P. Cocchini, D. Kirkpatrick, "Repeater scaling and its impact on CAD", IEEE Trans. on CAD, 23(4), 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.4
-
-
Saxena, P.1
Menezes, N.2
Cocchini, P.3
Kirkpatrick, D.4
-
18
-
-
0034867611
-
Scaling of stack effect and its application for leakage reduction
-
S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction", ISLPED 2001.
-
(2001)
ISLPED
-
-
Narendra, S.1
Borkar, S.2
De, V.3
Antoniadis, D.4
Chandrakasan, A.5
-
19
-
-
0030110490
-
Optimal wire sizing and buffer insertion for low power and a generalized delay model
-
J. Lillis, C.-K. Cheng, T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model", JSSC, 31(3), 1996.
-
(1996)
JSSC
, vol.31
, Issue.3
-
-
Lillis, J.1
Cheng, C.-K.2
Lin, T.Y.3
-
22
-
-
23044525393
-
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
-
C. Chu, D. Wong, "Closed form solution to simultaneous buffer insertion/sizing and wire sizing", TODAES 2001.
-
(2001)
TODAES
-
-
Chu, C.1
Wong, D.2
-
23
-
-
0029513451
-
A delay model for logic synthesis of continuously-sized networks
-
J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Y. Watanabe, "A delay model for logic synthesis of continuously-sized networks", ICCAD 1995.
-
(1995)
ICCAD
-
-
Grodstein, J.1
Lehman, E.2
Harkness, H.3
Grundmann, B.4
Watanabe, Y.5
-
24
-
-
0034478021
-
Simultaneous gate sizing and fanout optimization
-
W. Chen, C.-T. Hsieh, M. Pedram, "Simultaneous gate sizing and fanout optimization", ICCAD 2000.
-
(2000)
ICCAD
-
-
Chen, W.1
Hsieh, C.-T.2
Pedram, M.3
-
25
-
-
34748823693
-
The transient response of a damped linear network with particular regard to wideband amplifiers
-
W. C. Elmore, "The transient response of a damped linear network with particular regard to wideband amplifiers", J. Applied Physics, 19, 1948.
-
(1948)
J. Applied Physics
, vol.19
-
-
Elmore, W.C.1
-
28
-
-
29144462305
-
A fast fanout optimization for near-continuous buffer libraries
-
D. S. Kung, "A fast fanout optimization for near-continuous buffer libraries", DAC 1998.
-
(1998)
DAC
-
-
Kung, D.S.1
-
29
-
-
0034478021
-
Simultaneous gate sizing and fanout optimization
-
W. Chen, C.-T. Hsieh, M. Pedram, "Simultaneous gate sizing and fanout optimization", ICCAD 2000.
-
(2000)
ICCAD
-
-
Chen, W.1
Hsieh, C.-T.2
Pedram, M.3
-
30
-
-
84861296910
-
-
GNU Scientific Library (GSL), http://www.gnu.org/software/gsl/.
-
-
-
-
31
-
-
0036180537
-
Buffered Steiner trees for difficult instances
-
C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan, P. Villarrubia, "Buffered Steiner trees for difficult instances", IEEE Trans. on CAD, 21(1), 2002.
-
(2002)
IEEE Trans. on CAD
, vol.21
, Issue.1
-
-
Alpert, C.J.1
Hrkic, M.2
Hu, J.3
Kahng, A.B.4
Lillis, J.5
Liu, B.6
Quay, S.T.7
Sapatnekar, S.S.8
Sullivan, A.J.9
Villarrubia, P.10
-
32
-
-
84861300440
-
-
http://dropzone.tamu.edu/~cnsze/GSRC/ctree.html
-
-
-
|