Gate sizing and buffer insertion using economic models for power optimization

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 195-200

  Murugavel, Ashok K ^a   Ranganathan, N ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER INSERTION; GATE SIZING; POWER OPTIMAL CIRCUITS; POWER OPTIMIZATION;

ALGORITHMS; BUFFER CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; FREQUENCIES; FUNCTIONS; OPTIMIZATION; SWITCHING; VLSI CIRCUITS;

GATES (TRANSISTOR);

EID: 2342632486     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A.R. Conn, P.K. Coulman, R.A. Haring, G.L. Morrill and C. Visweswariah, "Optimization of custom MOS circuits by transistor sizing," in Proc. of IEEE/ACM Intl. Conf. on Computer-Aided Design, 1996, pp. 174-180.
2. M. Hashimoto, H. Onodera and K. Tamaru, "A practical gate resizing technique considering glitch reduction for low power design," in Proc. of Design Automation Conference, 1999, pp. 446-451.
3. S.S. Sapatnekar and W. Chuang, "Power-delay optimizations in gate sizing," ACM Trans. on Design Automation of Electronic Systems, vol. 5, no. 1, pp. 98-114, Jan. 2000.
4. V. Sundararajan, S.S. Sapatnekar and K.K. Parhi, "Fast and exact transistor sizing based on iterative relaxation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 5, pp. 568-581, May 2002.
5. K.S. Lowe and P.G. Gulak, "A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 5, pp. 419-434, May 1998.
6. Y. Jiang, S.S. Sapatnekar, C. Bamji and J. Kim, "Interleaving buffer insertion and transistor sizing into a single optimization," IEEE Trans. on VLSI Systems, vol. 6, no. 4, pp. 625-633, Dec. 1998.
7. S. Kim, J. Kim and S.-Y. Hwang, "New path balancing algorithm for glitch power reduction," in Proc. of IEE Circuits, Devices and Systems, 2001, pp. 151-156.
8. C. Chen and M. Sarrafzadeh, "Power reduction by simultaneous voltage scaling and gate sizing," in Proc. of Asia and South Pacific Design Automation Conf., 2000, pp. 333-338.
9. A.K. Murugavel and N. Ranganathan, "A game-theoretic approach for binding in behavioral synthesis," in Proc. of the Intl. Conf. on VLSI Design, 2003, pp. 452-458.
10. A.A. Lazar and N. Semret, "Auctions for Network Resource Sharing," Columbia University, Tech. Rep. CU/CTR/TR 468-97-02, 1997.
11. J.F. Nash, "The bargaining problem," Econometrica, vol. 18, no. 2, pp. 155-162, Apr. 1950.
12. K.O. Jeppson, "Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay," IEEE Journal on Solid State Circuits, vol. 29, no. 6, pp. 646-654, Jun. 1984.
13. J.B. Sulistyo and D.S. Ha, "Developing standard cells for TSMC 0.25um technology under MOSIS DEEP rules," Dept. of Electrical and Computer Engineering, Virginia Tech, Tech. Rep. VISC-2002-02, Apr. 2002.
14. R.D. McKelvey, A. McLennan and T. Turocy, Gambit: Software tools for game theory, ver 0.97 ed., California Inst. of Tech., Uni. of Minnesota and Texas A & M Uni., Sep. 2002.