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Volumn , Issue , 2004, Pages 361-366

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER OBSTACLES; FAST ALGORITHMS; ROUTING TREE CONSTRUCTION PROBLEMS; STOCHASTIC SEARCH SPACE;

EID: 2442473117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (17)
  • 1
    • 0029712263 scopus 로고    scopus 로고
    • Performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
    • J. Lillis, C. K. Cheng, T. T. Lin, C. Y. Ho, "Performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing", in Proc. ACM/IEEE Design Automation Conf., 1996, 395-400.
    • (1996) Proc. ACM/IEEE Design Automation Conf. , pp. 395-400
    • Lillis, J.1    Cheng, C.K.2    Lin, T.T.3    Ho, C.Y.4
  • 2
    • 0010352478 scopus 로고    scopus 로고
    • S-tree: A technique for buffered routing tree synthesis
    • M.Hrkic, J. Lillis, "S-Tree: A technique for Buffered routing tree synthesis", SASIMI, 2001, pp. 242-249.
    • (2001) SASIMI , pp. 242-249
    • Hrkic, M.1    Lillis, J.2
  • 3
    • 0036374274 scopus 로고    scopus 로고
    • Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages
    • M.Hrkic, J. Lillis, "Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages", in Proc. Int. Symp. Physical Design., 2002, pp. 98-103.
    • (2002) Proc. Int. Symp. Physical Design. , pp. 98-103
    • Hrkic, M.1    Lillis, J.2
  • 4
    • 0035212771 scopus 로고    scopus 로고
    • A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints
    • X. Tang, R. Tian, H. Xiang, and D. Wong, "A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints" in Proc. Int. Conf. Computer-Aided Design., 2001, pp. 49-56.
    • (2001) Proc. Int. Conf. Computer-aided Design. , pp. 49-56
    • Tang, X.1    Tian, R.2    Xiang, H.3    Wong, D.4
  • 6
    • 0030410359 scopus 로고    scopus 로고
    • Buffered steiner tree construction with wire sizing for interconnect layout optimization
    • Takumi Okamoto and Jason Cong. "Buffered Steiner tree construction with wire sizing for interconnect layout optimization". In Proc. IEEE Intl. Conf. on Computer-Aided Design, pages 44-49, 1996.
    • (1996) Proc. IEEE Intl. Conf. on Computer-aided Design , pp. 44-49
    • Okamoto, T.1    Cong, J.2
  • 9
    • 0032668895 scopus 로고    scopus 로고
    • Simultaneous routing and buffer insertion with restrictions on buffer locations
    • H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations", in Proc. ACM/IEEE Design Automation Conf., 1999. pp. 96-99.
    • (1999) Proc. ACM/IEEE Design Automation Conf. , pp. 96-99
    • Zhou, H.1    Wong, D.F.2    Liu, I.-M.3    Aziz, A.4
  • 10
    • 0033681635 scopus 로고    scopus 로고
    • Maze routing with buffer insertion and wiresizing
    • M.Lai and D. Wong, "Maze routing with buffer insertion and wiresizing", in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 374-378.
    • (2000) Proc. ACM/IEEE Design Automation Conf. , pp. 374-378
    • Lai, M.1    Wong, D.2
  • 12
    • 34748823693 scopus 로고
    • The transient response of damped linear networks with particular regard to wideband amplifiers
    • W. C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers", Journal of Applied Physics, 1948, 19:55-63.
    • (1948) Journal of Applied Physics , vol.19 , pp. 55-63
    • Elmore, W.C.1
  • 15
    • 0142054811 scopus 로고    scopus 로고
    • Bounds on number of slicing, mosaic, and general floorplans
    • October
    • Cien Shen and Chris Chu, "Bounds on Number of Slicing, Mosaic, and General Floorplans", IEEE TCAD, Vol. 22, No. 10, October 2003.
    • (2003) IEEE TCAD , vol.22 , Issue.10
    • Shen, C.1    Chu, C.2
  • 16
    • 0347761312 scopus 로고    scopus 로고
    • Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
    • C. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. Quay, "Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique", IEEE TCAD, 2004.
    • (2004) IEEE TCAD
    • Alpert, C.1    Chu, C.2    Gandham, G.3    Hrkic, M.4    Hu, J.5    Kashyap, C.6    Quay, S.7
  • 17
    • 2442471437 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
    • J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model", in Proc Int. Conf. Computer-Aided Design., 1996, pp. 134-139.
    • (1996) Proc Int. Conf. Computer-aided Design. , pp. 134-139
    • Lillis, J.1    Cheng, C.K.2    Lin, T.T.Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.