Wiresizing with buffer placement and sizing for power-delay tradeoffs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 346-351

  Shah, Jatan C ^a   Sapatnekar, Sachin S ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC PROGRAMMING; ELECTRIC WIRE; ELECTRIC WIRING; HEURISTIC METHODS; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING; SENSITIVITY ANALYSIS; TREES (MATHEMATICS);

JUDICIOUS APPROXIMATION; SHEET RESISTANCE;

VLSI CIRCUITS;

EID: 0029702518     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)