Adder methodology and design using probabilistic multiple carry estimates

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 6, 2005, Pages 697-703

  Ashmila, E M ^a   Dlay, S S ^a   Hinton, O R ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INDUCTION MOTORS; PERFORMANCE; PROBABILISTIC LOGICS;

ADDER CIRCUITS; CARRY LOOKAHEAD ELEMENTS; SPEED PERFORMANCE;

ADDERS;

EID: 27844582610     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045185     Document Type: Conference Paper

References (32)

1. Sun, X.-G., Mao, Z.-G., and Lai, F.-C.: 'A 64 bit parallel CMOS adder for high performance processors', Proc. IEEE Asia-Pacific Conf. on ASIC, 2002, pp. 205-208
2. Sakamoto, M., Hamano, D., and Morisue, M.: 'Design of a multiple-operand redundant binary adder', Syst. Comput. Jpn., 2002, 33, (10), pp. 1-9
3. Fang, C.-J., Huang, C.-H., Wang, J.-S., and Yeh, C.-W.: 'Fast and compact dynamic ripple carry adder design'. Proc. IEEE Asia-Pacific Conf. on ASIC, 2002, pp. 25-28
4. Kinniment, D.J.: 'An evaluation of asynchronous addition', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1996, 4, (1), pp. 137-140
5. Kong, B.-S., Im, J.-D., Kim, Y.-C., Jang, S.-J., and Jun, Y.-H.: 'CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI', IEE Proc., Circuits Devices Syst., 2003, 150, (1), pp. 45-50
6. Sklavos, N., and Koufopavlou, O.: 'Asynchronous low power VLSI implementation of the international data encryption algorithm'. 8th IEEE Int. Conf. on Electronics, Circuits and Systems, 2001, 3, pp. 1425-1428
7. Singh, M., and Nowick, S.M.: 'Fine-grain pipelined asynchronous adders for high-speed DSP applications'. Proc. IEEE Computer Society Workshop on VLSI, System Design for a System-on-Chip Era, 2000, pp. 111-118
8. Beerel, P.A.: 'Asynchronous circuits: an increasingly practical design solution'. Proc. IEEE Computer Society Int. Symp. on Quality Electronic Design, 2002, pp. 367-372
9. Brunvand, E., Nowick, S., and Yun, K.: 'Practical advances in asynchronous design and in asynchronous/synchronous interfaces'. Proc. IEEE Design Automation Conf., 1999, pp. 104-109
10. Allier, E., Fesquet, L., Renaudin, M., and Sicard, G.: 'Low-power asynchronous A/D conversion'. Proc. Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th Int. Workshop, PATMOS, 2002, pp. 81-91
11. Siu, P.-L., Choy, C.-S., Butas, J., and Chan, C.F.: 'A low power asynchronous DES'. Proc. IEEE Int. Symp. on Circuits and Systems, 2001, 4, pp. 538-541
12. Hauck, S.: 'Asynchronous design methodologies an overview', Proc. IEEE, 1995, 83, (1), pp. 69-93
13. Johnson, D., and Akella, V.: 'Design and analysis of asynchronous adders', IEE Proc., Comput. Digit. Tech., 1998, 145, (1), pp. 1-7
14. Davis, A., and Nowick, S.M.: 'Introduction to asynchronous circuit design' (University of Utah Technical Report, Department of Computer Science, UUCS-97-013, Sept 1997)
15. Chou, W., Beerel, P., Ginosar, R., Kol, R., Myers, C., Rotem, S., Stevens, K., and Yun, K.: 'Average-case optimized technology mapping of one-hot domino circuit'. Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, 1998, pp. 80-91
16. Donaghy, D., Brackenbury, L., and Hall, S.: 'Combining SOI technology and asynchronous design for power reduction'. Silicon-on-Insulator Technology and Devices X, Proc. Tenth Int. Symp., (Electrochem. Soc., 2001), pp. 337-342
17. Nowick, S.M.: 'Design of a Low-latency a synchronous adder using speculative completion', IEE Proc., Comput. Digit. Tech., 1996, 143, (5), pp. 301-307
18. Cheng, F.-C., Unger, S.H., and Theobald, M.: 'Self-timed carry-lookahead adders', IEEE Trans. Comput., 2000, 49, (7), pp. 659-672
19. Andreev, B.D., Titlebaum, E., and Friedman, E.: 'Tapered transmission gate chains for improved carry propagation'. IEEE Proc. 45th Midwest Symp. on Circuits and Systems, 2002, III, pp. 449-452
20. Han, K.-N., Han, S.-W., and Yoon, E.: 'A new adder scheme with reduced P, G signal generations using redundant binary number system'. Proc. IEEE Int. Symp. on Circuits and Systems, 2000, 5, pp. 633-636
21. Weinberger, A., and Smith, J.L.: 'A logic for high-speed addition', National Bureau of Standards, Circular 591, 1958, pp. 3-12
22. Hwang, K.: 'Computer arithmetic: principles, architecture, and design' (John Wiley & Sons, New York, 1979)
23. Shoji, M.: 'CMOS digital circuit technology' (Englewood Cliffs, New Jersey, Prentice-Hall, 1988)
24. Franklin, M.A., and Pan, T.: 'Performance comparison of asynchronous adders'. Proc. IEEE Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, ASYNC-94, 1994, pp. 117-125
25. Nagendra, C., Irwin, M., and Owens, R.: 'Area-time-power trade-offs in parallel adders', IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 1996, 43, (10), pp. 689-702
26. Bedrij, O.J.: 'Carry select adder', IRE Trans. Electron. Comput., 1962, EC11, pp. 340-346
27. Parhami, B.: 'Computer arithmetic: algorithms and hardware designs' (Oxford University Press, Oxford, UK, 2000)
28. Chang, T.Y., and Hsiao, M.J.: 'Carry select adder using single ripple carry adder', Electron. Lett., 1998, 34, pp. 2101-2103
29. Hashemian, R.: 'A new design for high speed and high-density carry select adders'. Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, 2000, 3, pp. 1300-1303
30. Liao, M.-J., Su, C.-F., Chang, C.-Y., and Wu, A.C.-H.: 'A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers', IEEE Int. Symp. on Circuits and Systems, 2002, 1, I-81-84
31. Wallace, W.F., Dlay, S., and Hinton, O.: 'Probabilistic carry estimate for improved asynchronous adder performance', IEE Proc., Comput. Digit. Tech., 2001, 148, (6), pp. 221-226
32. Wang, C.C., Tseng, Y.L., Lee, P.M., Lee, R.C., and Huang, C.J.: 'A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic', IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 2003, 50, (9), pp. 1208-1216