Fast and compact dynamic ripple carry adder design

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 25-28

  Fang, Chih Jen ^a   Huang, Chung Hsun ^a   Wang, Jinn Shyan ^a   Yeh, Ching Wei ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; DESIGN; RECONFIGURABLE HARDWARE;

CMOS TECHNOLOGY; CRITICAL PATHS; DIFFERENTIAL CASCODE VOLTAGE SWITCHES; DYNAMIC CIRCUITS; FUNDAMENTAL BUILDING BLOCKS; HIGH SPEED; RIPPLE CARRY ADDERS; SPICE SIMULATIONS;

ADDERS;

EID: 84966293828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031523     Document Type: Conference Paper

References (6)

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3. Gustavo A. Ruiz, "Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits". IEEE Journal of Solid-State Circuits, Vol. 33, NO. 4, April 1998.
4. Chang, T.-Y. and Hsiao, M. J., "Carry-select adder using single ripple-carry adder". Electronics Letters, Volume: 34, Issue: 22, 29 Oct. 1998, Pages: 2101-2103
5. Youngjoon Kim and Lee-Sup Kim, "A low power carry select adder with reduced area". Circuits and systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Volume: 4, 2001. Pages: 218-221.
6. Youngjoon Kim and Lee-Sup Kim, "64-bit carry-select adder with reduced area". Electronics Letters, Volume: 37 Issue: 10, 10 May 2001. Pages: 614-615.