Average-case optimized technology mapping of one-hot domino circuits

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 80-91

  Chou, Wei Chun ^a   Beerel, Peter A ^a   Ginosar, Ran ^b,d   Kol, Rakefet ^b   Myers, Chris J ^c   Rotem, Shai ^d   Stevens, Kenneth ^d   Yun, Kenneth Y ^e  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^c UNIVERSITY OF UTAH   (United States)

^d INTEL CORPORATION   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DECODING; MAPPING; TIMING CIRCUITS;

AVERAGE CASE; CRITICAL PATHS; DOMINO CIRCUIT; DOMINO LOGIC; INPUT PATTERNS; INTEGRAL COMPONENTS; MAPPING TECHNIQUES; TECHNOLOGY MAPPING;

DELAY CIRCUITS;

EID: 33749763157     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666496     Document Type: Conference Paper

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