A 64 bit parallel CMOS adder for high performance processors

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 205-208

  Sun, Xu Guang ^a   Mao, Zhi Gang ^a   Lai, Feng Chang ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

Binary parallel adder; clock delayed domino logic; dynamic compound gate

Indexed keywords

BINS; CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; RECONFIGURABLE HARDWARE;

ADDER ARCHITECTURE; CMOS TECHNOLOGY; DOMINO LOGIC; DSP PROCESSOR; DYNAMIC COMPOUND; HIGH PERFORMANCE PROCESSORS; HIGH-PERFORMANCE MICROPROCESSORS; PARALLEL ADDERS;

ADDERS;

EID: 84966293806     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031568     Document Type: Conference Paper

References (12)

1. K. Udea, N. Sasaki, H. Sato, and K. Mashiko. A 64-bit carry took ahead using pass transistor BiCMOS gate. IEEE Journal of Solid-State Circuits, Vol.31, pp.810-817, 1996.
2. K. Suzuki et al. A 500MHz 32bit 0.4μm CMOS RISC Processor. IEEE Journal of Solid-State Circuits, Vol.29, No.12, pp.1464-1473, 1994
3. J. L. Hennessy, D. A. Patterson, Computer Organization & Design the Hardware/Software Interface. China Machine Press, Beijing, 1999.
4. R. P. Brent, H. T. Kung. A Regular Layout for Parallel Adders, IEEE Trans. on Computers, Vol.31, No.3, pp.260-264, 1982.
5. T. P. Kelliher et al. ELM - A Fast Addition Algorithm Discovered by a Program. IEEE Trans. on Computers, Vol.41, No.9, pp.1181-1184, 1992.
6. P. M. Kogge, H. S. Stone. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. IEEE Trans. on Computers, Vol.22, No.8, pp.786-792, 1973.
7. S. Naffziger. A Sub-Nanosecond 0.5um 64b Adder Design. IEEE International Solid-State Circuits Conference, pp.362-363, 1996.
8. K. Bernstein et al. High Speed CMOS Design Styles. Kluwer Academic Publishers, Norwell, 1998.
9. Masakazu. FET Scaling in Domino CMOS Gates. IEEE Journal of Solid-State Circuits, Vol. SC-20, No.5, pp. 1067-1071, 1985.
10. Larry T. Wurtz. An Efficient Scaling procedure for Domino CMOS Logic. IEEE Journal of Solid-State Circuits. Vol. 28, No. 9, pp. 979-982, 1993.
11. Simon Knowles. A Family of Adders. Proceedings of 15th IEEE Symposium on Computer Arithmetic, pp.277-284, 2001.
12. H. Lindkwist, P. Andersson. Dynamic CMOS Circuit Techniques for Delay and Power Reduction in Parallel Adder. 16th Conference on Advanced Research in VLSI, pp.121-130, 1995.