Probabilistic carry state estimate for improved asynchronous adder performance

IEE Proceedings: Computers and Digital Techniques

Volumn 148, Issue 6, 2001, Pages 221-226

  Wallace, W F ^a   Dlay, S S ^a   Hinton, O R ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; PROBABILITY; STATE ESTIMATION; VLSI CIRCUITS;

ASYNCHRONOUS CIRCUITS; CARRY LOOKAHEAD ADDER; CARRY SELECT LOOKAHEAD; CARRY STATE ESTIMATE; EQUIVALENT RIPPLE;

ADDERS;

EID: 0035520938     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20010781     Document Type: Article

References (12)

1. Checked carry select adder
2. A CMOS floating point multiplier
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4. Statistical carry lookahead adders
5. An evaluation of asynchronous addition
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7. Speculative completion for the design of high performance asynchronous adders ASYNC-97
8. A CMOS VLSI implementation of an asynchronous ALU
9. The improvement of conditional sum adder for low power applications
10. An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture
11. Low-energy CSMT carry generators and binary adders
12. Design and analysis of asynchronous adders