Area-time-power tradeoffs in parallel adders

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 10, 1996, Pages 689-702

  Nagendra, Chctana ^a   Irwin, Mary Jane ^b   Owens, Robert Michael ^a  

^a ADVANCED MICRO DEVICES   (United States)

^b The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SHORT CIRCUIT CURRENTS;

LINEAR TIME RIPPLE; MANCHESTER CARRY ADDERS; PARALLEL ADDERS;

ADDERS;

EID: 0030264539     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.539001     Document Type: Article

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