A carry-select-adder optimization technique for high-performance booth-encoded Wallace-tree multipliers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 81-84

  Liao, M J ^a   Su, C F ^a   Chang, C Y ^a   Wu, Allen C H ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CARRY LOGIC; ENCODING (SYMBOLS); HEURISTIC METHODS; LOGIC DESIGN; MULTIPLYING CIRCUITS; OPTIMIZATION; TREES (MATHEMATICS);

CARRY SELECT ADDER; DATA ARRIVAL TIMES; PARTIAL PRODUCT REDUCTION TREE; WALLACE TREE MULTIPLIER;

ADDERS;

EID: 0036280706     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009782     Document Type: Article

References (12)

1. A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
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5. M*N booth encoded multiplier generator using optimized Wallace trees
6. Design strategies for the final adder in a parallel multiplier
7. Implementing multiply-accumulate operation in multiplication time
8. Optimal circuits for parallel multipliers
9. A signed binary multiplication technique
10. High-speed arithmetic in binary computers