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Volumn 3, Issue , 2002, Pages

Tapered transmission gate chains for improved carry propagation

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTROMAGNETIC WAVE PROPAGATION; GATES (TRANSISTOR);

EID: 18744436827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (14)
  • 1
    • 0012977957 scopus 로고
    • The transmission gate: An advantage of CMOS gate-arrays
    • May
    • G. Bouhasin, "The Transmission Gate: An Advantage of CMOS Gate-Arrays," Journal of Semicustom ICs, Vol. 2, No, 3, pp. 16-22, May 1985.
    • (1985) Journal of Semicustom ICs , vol.2 , Issue.3 , pp. 16-22
    • Bouhasin, G.1
  • 3
    • 0026851438 scopus 로고
    • An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit
    • November
    • T. Sato et al., "An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit," IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 657-659, November 1993.
    • (1993) IEEE Journal of Solid-State Circuits , vol.27 , Issue.4 , pp. 657-659
    • Sato, T.1
  • 6
    • 0002201010 scopus 로고
    • A unified design methodology for CMOS tapered buffers
    • March
    • B. Cherkauer and E. G. Friedman, "A Unified Design Methodology for CMOS Tapered Buffers," IEEE Transactions on VLSI, Vol. 3, No. 1, pp. 99-111, March 1995.
    • (1995) IEEE Transactions on VLSI , vol.3 , Issue.1 , pp. 99-111
    • Cherkauer, B.1    Friedman, E.G.2
  • 7
    • 0029244747 scopus 로고
    • Design of tapered buffers with local interconnect capacitance
    • February
    • B. Cherkauer and E. G. Friedman, "Design of Tapered Buffers with Local Interconnect Capacitance," IEEE Journal of Solid-State Circuits, Vol. 30, No. 2, pp. 151-155, February 1995.
    • (1995) IEEE Journal of Solid-State Circuits , vol.30 , Issue.2 , pp. 151-155
    • Cherkauer, B.1    Friedman, E.G.2
  • 10
    • 0024092480 scopus 로고
    • Explicit formulation of delays in CMOS data paths
    • October
    • D. Deschacht, M. Robert, and D. Auvergne, "Explicit Formulation of Delays in CMOS Data Paths," IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1257-1264, October 1988.
    • (1988) IEEE Journal of Solid-State Circuits , vol.23 , Issue.5 , pp. 1257-1264
    • Deschacht, D.1    Robert, M.2    Auvergne, D.3
  • 11
    • 0024177601 scopus 로고
    • Macromodeling CMOS circuits for timing simulation
    • December
    • L. Brocco et al., Macromodeling CMOS Circuits for Timing Simulation," IEEE Transactions on Computer-Aided Design, Vol. 7, No. 12, pp. 1237-1249, December 1988.
    • (1988) IEEE Transactions on Computer-Aided Design , vol.7 , Issue.12 , pp. 1237-1249
    • Brocco, L.1
  • 12
    • 0013029764 scopus 로고
    • Delay macromodelling of CMOS transmission-gate-based circuits
    • March
    • S. Vemuru, "Delay Macromodelling of CMOS Transmission-Gate-Based Circuits," International Journal of Modelling and Simulation, Vol. 15, No, 3, pp. 90-97, March 1995.
    • (1995) International Journal of Modelling and Simulation , vol.15 , Issue.3 , pp. 90-97
    • Vemuru, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.