CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI

IEE Proceedings: Circuits, Devices and Systems

Volumn 150, Issue 1, 2003, Pages 45-50

  Kong, B S ^a   Im, J D ^b   Kim, Y C ^b   Jang, S J ^b   Jun, Y H ^b  

^a Hankuk Aviation University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; EQUIVALENT CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MOSFET DEVICES; VLSI CIRCUITS;

CLOCK FREQUENCY; DIFFERENTIAL LOGIC; POWER DISSIPATION; POWER REDUCTION;

CMOS INTEGRATED CIRCUITS;

EID: 0037317917     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030271     Document Type: Article

References (8)

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