A limit study on the potential of compression for improving memory system performance, power consumption, and cost

Journal of Instruction-Level Parallelism

Volumn 7, Issue , 2005, Pages

  Mahapatra, Nihar R ^a   Liu, Jiangjiang ^b   Sundaresan, Krishnan ^a   Dangeti, Srinivas ^c   Venkatrao, Balakrishna V ^c  

^a Michigan State University   (United States)

^b Rice University   (United States)

^c SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27444443153     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (65)

1. D. Culler, J. Singh, and A. Gupta, Parallel Computer Architecture. Morgan Kaufmann Publishers Inc., 1999.
2. J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Third edition. Morgan Kaufmann Publishers Inc., 2003.
3. P. Sotiriadis and A. Chandrakasan, "Low Power Bus Coding Techniques Considering Inter-Wire Capacitances," in Proceedings of Custom Integrated Circuits Conference, pp. 414-419, May 2000.
4. W. Wolf, Computers as Components: Principles of Embedded Computing System Design. Morgan Kaufmann Publishers Inc., 2001.
5. B. Cmelik and D. Keppel, "SHADE: A Fast Instruction-Set Simulator for Execution Profiling," ACM SIGMETRICS Performance Evaluation Review, vol. 22, pp. 128-137, May 1994.
6. P. Shivakumar and N. Jouppi, "CACTI 3.0: An Integrated Cache Cycle Timing, Power, and Area Model," Tech. Rep. WRL Research Report 2001/2, Compaq Western Research Laboratory, Aug. 2001.
7. Y. Zhang, R. Y. Chen, W. Ye, and M. Irwin, "System Level Interconnect Power Modeling," in IEEE International ASIC/SoC Conference, pp. 289-293, Sept. 1998.
8. A. Park and M. Farrens, "Address Compression through Base Register Caching," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 193-199, Nov. 1990.
9. M. Farrens and A. Park, "Dynamic Base Register Caching: A Technique for Reducing Address Bus Width," in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 128-137, May 1991.
10. D. Citron and L. Rudolph, "Creating a Wider Bus using Caching Techniques," in Proceedings of International Symposium on High Performance Computer Architecture, pp. 90-99, Jan. 1995.
11. J. Liu, N. Mahapatra, and K. Sundaresan, "Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study," in Proceedings of IEEE International Conference on Computer Design, pp. 458-464, Oct. 2004.
12. D. Hammerstrom and E. Davidson, "Information Content of CPU Memory Referencing Behavior," in Proceedings of the 4th Annual Symposium on Computer Architecture, pp. 184-192, ACM Press, 1977.
13. J. Becker, A. Park, and M. Farrens, "An Analysis of the Information Content of Address Reference Streams," in Proceedings of the International Conference on Microarchitecture, pp. 19-24, Nov. 1991.
14. J. Wang and R. Quong, "The Feasibility of Using Compression to Increase Memory System Performance," in Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems, pp. 107-113, Jan. 1994.
15. M. Kozuch and A. Wolfe, "Compression of Embedded System Programs," in Proceedings of International Conference on Computer Design, pp. 270-277, Oct. 1994.
16. M. Kjelso, M. Gooch, and S. Jones, "Empirical Study of Memory-Data: Characteristics and Compressibility," IEE Proceedings on Computers and Digital Techniques, vol. 145, pp. 63-67, Jan. 1998.
17. J. Liu, N. Mahapatra, K. Sundaresan, S. Dangeti, and B. Venkatrao, "Memory System Compression and Its Benefits," in Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, pp. 41-45, Sept. 2002.
18. N. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B. Venkatrao, "The Potential of Compression to Improve Memory System Performance, Power Consumption, and Cost," in Proceedings of IEEE Performance, Computing and Communications Conference, pp. 343-350, Apr. 2003.
19. D. Citron, "Exploiting Low Entropy to Reduce Wire Delay," Computer Architecture Letters, vol. 3, Jan. 2004.
20. K. Basu, A. Choudhary, J. Pisharath, and M. Kandemir, "Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 19-24, Nov. 2002.
21. K. Kant and R. Iyer, "Design and Performance of Compressed Interconnects for High Performance Servers," in Proceedings of International Conference on Computer Design, pp. 164-169, Oct. 2003.
22. C. Fraser, E. Myers, and A. Wendt, "Analyzing and Compressing Assembly Code," SIGPLAN Notices, vol. 19, pp. 117-121, June 1984.
23. J. Ernst, W. Evans, C. Fraser, S. Lucco, and T. Proebsting, "Code Compression," in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 358-365, June 1997.
24. D. Kirovski, J. Kin, and W. Mangione-Smith, "Procedure Based Program Compression," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 204-213, Dec. 1997.
25. K. Cooper and N. McIntosh, "Enhanced Code Compression for Embedded RISC Processors," in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 139-149, May 1999.
26. S. Debray, W. Evans, R. Muth, and B. de Sutter, "Compiler Techniques for Code Compaction," Transactions on Programming Languages and Systems, vol. 22, pp. 378-415, Mar. 2000.
27. A. Wolfe and A. Channin, "Executing Compressed Programs on an Embedded RISC Architecture," in Proceedings of the Annual Symposium on Computer Architecture, pp. 81-91, Dec. 1992.
28. S. Liao, S. Devadas, and K. Keutzer, "Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques," in Proceedings of Conference on Advanced Research in VLSI, pp. 393-399, Mar. 1995.
29. C. Lefurgy and T. Mudge, "Code Compression for DSP," Tech. Rep. CSE-TR-380-98, EECS Department, University of Michigan, Ann Arbor, MI, 1998.
30. H. Lekatsas and W. Wolf, "Random Access Decompression using Binary Arithmetic Coding," in Prodeedings of Data Compression Conference, pp. 306-315, Mar. 1999.
31. H. Lekatsas, J. Henkel, and W. Wolf, "Code Compression for Low Power Embedded System Design," in Proceedings of Annual ACM/IEEE Design Automation Conference, pp. 294-299, June 2000.
32. T. Kemp, R. Montoye, J. Harper, J. Palmer, and D. Auerbach, "A Decompression Core for PowerPC," IBM Journal of Research and Development, vol. 42, pp. 807-811, Nov. 1998.
33. M. Game and A. Booker, "Codepack™ Code Compression for PowerPC Processors." http://www-3.ibm.com/chips, May 2000.
34. K. Sundaresan and N. Mahapatra, "Code Compression Techniques for Embedded Systems and Their Effectiveness," in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 262-263, Feb. 2003.
35. T. M. Conte, S. Banerjia, S. Y. Larin, K. N. Menezes, and S. W. Sathaye, "Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 201-211, Dec. 1996.
36. Y. Xie, W. Wolf, and H. Lekatsas, "Code Compression for VLIW Using Variable-to-Fixed Coding," in Proceedings of the International Symposium on System Synthesis, pp. 138-143, Oct. 2002.
37. J. Hoogerbrugge, L. Augusteijn, J. Trum, and R. van de Wiel, "A Code Compression System Based on Pipelined Interpreters," Software Practice and Experience, vol. 29, no. 11, pp. 1005-1023, 1999.
38. Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," in Proceedings of International Symposium on Low Power Electronics and Design, pp. 265-268, Aug. 1997.
39. L. Benini, G. D. Micheli, E. Macii, and M. Poncino, "Selective Instruction Compression for Memory Energy Reduction in Embedded Systems," in Proceedings of International Symposium on Low Power Electronics and Design, pp. 206-211, Aug. 1999.
40. I. Kadayif and M. Kandemir, "Instruction Compression and Encoding for Low-Power Systems," in Proceedings of the IEEE International ASIC/SOC Conference (ASIC/SOC'02), pp. 301-305, Sept. 2002.
41. Advanced RISC Machines Ltd (ARM), An Introduction to Thumb, Mar. 1995. http://www.arm.com.
42. K. Kissell, "MIPS16: High-density MIPS for the Embedded Market." http://www.mips.com, 1997.
43. R. B. Tremaine, P. Franaszek, J. Robinson, C. Schulz, T. Smith, M. Wazlowski, and P. Bland, "IBM Memory eXpansion Technology (MXT)," IBM Journal of Research and Development, vol. 45, pp. 271-285, Mar. 2001.
44. P. Franaszek and J. Robinson, "Design and Analysis of Internal Organizations for Compressed Random Access Memories," Tech. Rep. IBM Research Report RC 21146(94535)20OCT98, IBM Research Division, T.J. Watson Research Center, Yorktown Heights, NY, Oct. 1998.
45. J.-S. Lee, W.-K. Hong, and S.-D. Kim, "Design and Evaluation of a Selective Compressed Memory System," in Proceedings of International Conference on Computer Design, pp. 184-191, Oct. 1999.
46. J. Yang, Y. Zhang, and R. Gupta, "Frequent Value Compression in Data Caches," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 258-265, Nov. 2000.
47. L. Villa, M. Yang, and K. Asanovic, "Dynamic Zero Compression for Cache Energy Reduction," in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 214-220, Dec. 2000.
48. A. Alameldeen and D. Wood, "Adaptive Cache Compression for High-Performance Processors," in Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA'04), pp. 212-222, IEEE Computer Society, 2004.
49. E. Hallnor and S. Reinhardt, "A Unified Compressed Memory Hierarchy," in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 201-212, IEEE Computer Society, 2005.
50. C. Su, C. Tsui, and A. Despain, "Low Power Architecture Design and Compilation Techniques for High-Performance Processors," Tech. Rep. ACAL-TR-94-01, Advanced Computer Architecture Laboratory, University of Southern California, 1994.
51. M. Stan and W. Burleson, "Bus-Invert Coding for Low-Power I/O," IEEE Transactions on VLSI Systems, vol. 3, pp. 49-58, Mar. 1995.
52. L. Benini, G. D. Micheli, E. Macii, D. Sciuto, and C. Silvano, "Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems," in Proceedings of Great Lakes Symposium on VLSI, pp. 77-82, Mar. 1997.
53. E. Musoll, T. Lang, and J. Cortadella, "Working-Zone Encoding for Reducing the Energy in Microprocessor Address Buses," IEEE Transactions on VLSI Systems, vol. 6, pp. 568-572, Dec. 1998.
54. T. Lang, E. Musoll, and J. Cortadella, "Extension of the Working-Zone Encoding Method to Reduce the Energy on the Microprocessor Data Bus," in Proceedings of International Conference on Computer Design, pp. 414-419, Oct. 1998.
55. W.-C. Cheng and M. Pedram, "Memory Bus Encoding for Low-Power: A Tutorial," in Proceedings of International Symposium on Quality of Electronics Design, pp. 199-204, Mar. 2001.
56. Y. Aghaghiri, F. Fallah, and M. Pedram, "Irredundant Address Bus Encoding for Low Power," in Proceedings of International Symposium on Low Power Electronics and Design, pp. 322-327, ACM Press, NY, USA, Aug. 2001.
57. 2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs," in Proceedings of Annual ACM/IEEE Design Automation Conference, pp. 744-749, June 2001.
58. P. Sotiriadis and A. Chandrakasan, "Reducing Bus Delay in Sub-Micron Technology Using Coding," in Proceedings of Asia and South Pacific Design Automation Conference, pp. 109-114, Jan. 2001.
59. B. Victor and K. Keutzer, "Bus Encoding to Prevent Crosstalk Delay," in Proceedings of IEEE International Conference on Computer-Aided Design, pp. 57-63, Nov. 2001.
60. SPEC, "SPEC CPU2000 Benchmark Suite Verl.2." http://www.specbench.org/cpu2000, 2000.
61. C. Lee, M. Potkonjak, and W. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems," in Proceedings of the Annual Symposium on Computer Architecture, pp. 330-335, June 1997.
62. K. Skadron, P. Ahuja, M. Martonosi, and D. Clark, "Selecting a Single, Representative Sample for Accurate Simulation of SPECint Benchmarks," IEEE Transactions on Computers, vol. 48, pp. 1260-1281, Nov. 1999.
63. H. Lekatsas and W. Wolf, "SAMC: A Code Compression Algorithm for Embedded Processors," IEEE Transactions on Computer-aided Design, vol. 18, pp. 1689-1701, Dec. 1999.
64. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. Irwin, "The Design and Use of Simplepower: A Cycle-Accurate Energy Estimation Tool," in Proceedings of Annual ACM/IEEE Design Automation Conference, pp. 340-345, June 2000.
65. D. Weaver and T. Germond, eds., The SPARC Architecture Manual, Version 9. Prentice Hall, 2000.