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Volumn 2001-January, Issue , 2001, Pages 199-204

Memory bus encoding for low power: A tutorial

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; POWER MANAGEMENT;

EID: 4444376574     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915227     Document Type: Conference Paper
Times cited : (37)

References (21)
  • 4
  • 5
    • 0033720602 scopus 로고    scopus 로고
    • Bus encoding for low power high-performance memory systems
    • N. Chang, K. Kim, and J. Cho, "Bus encoding for low power high-performance memory systems," Proc. of Design Automation Conf, pp. 800-805, 2000.
    • (2000) Proc. of Design Automation Conf , pp. 800-805
    • Chang, N.1    Kim, K.2    Cho, J.3
  • 10
    • 0033341913 scopus 로고    scopus 로고
    • Low power chip interface based on bus data encoding with adaptive codebook method
    • S. Komatsu, M. Ikeda and K. Asada, "Low power chip interface based on bus data encoding with adaptive codebook method," Proc. of the Ninth Great Lakes Symp. on VLSI, pp. 368-371, 1999.
    • (1999) Proc. of the Ninth Great Lakes Symp. on VLSI , pp. 368-371
    • Komatsu, S.1    Ikeda, M.2    Asada, K.3
  • 11
    • 0032628047 scopus 로고    scopus 로고
    • A coding framework for low-power address and data busses
    • June
    • S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. on VLSI, Vol. 7, No. 2, pp. 212-221, June 1999.
    • (1999) IEEE Trans. on VLSI , vol.7 , Issue.2 , pp. 212-221
    • Ramprasad, S.1    Shanbhag, N.R.2    Hajj, I.N.3
  • 12
  • 20
    • 0028715171 scopus 로고
    • Saving power in the control path of embedded processors
    • C. L. Su, C. Y. Tsui, and A. M. Despain, "Saving power in the control path of embedded processors," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 24-30, 1994.
    • (1994) IEEE Design and Test of Computers , vol.11 , Issue.4 , pp. 24-30
    • Su, C.L.1    Tsui, C.Y.2    Despain, A.M.3
  • 21
    • 84941356767 scopus 로고    scopus 로고
    • Interleaving partial bus-invert coding for low power reconfiguration of FPGAs
    • S. Yoo and K. Choi, "Interleaving partial bus-invert coding for low power reconfiguration of FPGAs," Proc. of the Sixth Int'l Conf. on VLSI and CAD, pp. 549-552, 1999.
    • (1999) Proc. of the Sixth Int'l Conf. on VLSI and CAD , pp. 549-552
    • Yoo, S.1    Choi, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.