A decompression core for PowerPC

IBM Journal of Research and Development

Volumn 42, Issue 6, 1998, Pages 807-811

  Kemp, T M ^a   Montoye, R K ^a   Harper, J D ^a   Palmer, J D ^a   Auerbach, D J ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER SYSTEMS PROGRAMMING; EMBEDDED SYSTEMS; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS; PERSONAL COMPUTERS; PROGRAM COMPILERS;

ON-THE-FLY HARDWARE DECOMPRESSION;

DATA COMPRESSION;

EID: 0032207443     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.426.0807     Document Type: Article

References (5)

1. http://www.intel.com/intel/museum/25anniv/html/hof/moore.htm .
2. The PowerPC Architecture: A Specification for a New Family of RISC Processors, C. May, Ed., ISBN 1-55860-316-6, Morgan Kaufmann Publishers, San Francisco, 1994.
3. Joint Testing Architecture Group, IEEE Standard No. 1149.1-1990, American National Standards Institute, Washington, DC, 1990.
4. Willard L. Eastman, Abraham Lempel, Jacob Ziv, and Martin Cohn, "Apparatus and Method for Compressing Data Signals and Restoring the Compressed Data Signals," U.S. Patent 4,464,650, August 7, 1984.
5. D. A. Huffman, "A Method for the Construction of Minimum-Redundancy Codes," Proc. IRE 40, No. 9, 1098-1101 (1952).