Memory system compression and its benefits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 41-45

  Liu, Jiangjiang ^a   Mahapatra, Nihar R ^a   Sundaresan, Krishnan ^a   Dangeti, Srinivas ^b   Venkatrao, Balakrishna V ^b  

^a State University of New York   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Address compression; Bandwidth; Cache; Cost effective design; Data compression; Entropy; Instruction compression; Latency; Lossless compression; Low power; Markov models; Memory; Register Hie; Storage; Traffic

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; BANDWIDTH COMPRESSION; CACHE MEMORY; COST BENEFIT ANALYSIS; COST EFFECTIVENESS; COSTS; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC; DIGITAL STORAGE; ELECTRIC POWER UTILIZATION; ENERGY STORAGE; ENTROPY; INTEGER PROGRAMMING; MARKOV PROCESSES; TELECOMMUNICATION TRAFFIC;

CACHE; COST EFFECTIVE DESIGN; LATENCY; LOSSLESS COMPRESSION; LOW POWER; MARKOV MODEL; REGISTER HIE;

DATA COMPRESSION;

EID: 84949475159     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158028     Document Type: Conference Paper

References (26)

1. Advanced RISC Machines. An Introduction to Thumb, March 1995. Available at: http://www.arm.com
2. J.C. Becker, A. Park, and M. Farrens. An Analysis of the Information Content of Address Reference Streams. In Proceedings of the International Conference on Microarchitecture, pages 19-24. November 1991.
3. W,-C. Cheng and M. Pedram. Memory Bus Encoding for Low-power: A Tutorial. In Proceedings of International Symposium on Quality of Electronics Design, March 2001.
4. D. Citron and L. Rudolph. Creating a Wider Bus using Caching Techniques. In Proceedings of International Symposium on High Performance Computer Architecture, pages 90-99, January 1995.
5. B. Cmelik and D. Keppel. SHADE: A Fast Instruction-set Simulator for Execution Profiling. ACM SIGMETR1CS Performance Evaluation Review, 22(l):l28-l37, May 1994.
6. P.A. Franaszek and J.T. Robinson. Design and Analysis of Internal Organizations for Compressed Random Access Memories. Technical Report IBM Research Report RC 21146(94535)20OCT98, IBM Research Division, T.J. Walson Research Center, Yorktown Heights. NY, October 1998.
7. J.L. Hennessey and D.A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., 1996.
8. K.D. Kissell. M1PS16: High-density MIPS for the Embedded Market. http://www.mips.com/Documentation/MIPS16whitepaper.pdf, 1997.
9. M. Kjelso, M. Gooch, and S. Jones. Empirical Study of Memory-data: Characteristics and Compressibility. 1EE Proceedings on Computers and Digital Techniques, 145(1):63-67, January 1998.
10. M. Kozuch and A. Wolfe. Compression of Embedded System Programs. In Proceedings of International Conference on Computer Design, 1994.
11. J.-S. Lee, W.-K. Hong, and S.-D. Kim. Design and Evaluation of a Selective Compressed Memory System, In Proceedings of International Conference on Computer Design, pages 184-191, 1999.
12. C. Lefurgy, P. Bird, I.C. Chen, and T. Mudge. Improving Code Density Using Compression Techniques. In Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, December 1997.
13. H. Lekatsas and W. Wolf. Code Compression for Embedded Systems. In Proceedings of Annual ACM/IEEE Design Automation Conference, pages 516-521, June 1998.
14. H. Lekatsas and W. Wolf. SAMC: A Code Compression Algorithm for Embedded Processors. IEEE Transactions on Computer-aided Design, 18(12):1689-1701, December 1999.
15. S.Y. Liao, S. Devadas, and K. Keutzer. Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques. In Proceedings of Conference on Advanced Research in VLSI. March 1995.
16. N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao. An Analysis of the Potential of Compression in Improving Memory System Performance, Power Consumption, and Cost. In Proceedings of the Second Annuui Workshop on Memory Performance Issues (WMPI 2002), May 2002.
17. N.R. Mahapatra, J. Liu, K. Sundaresan. S. Dangeti, and B.V. Venkatrao. The Performance Advantage of Applying Compression to the Memory System. In Proceedings of the ACM-SIGPLAN Workshop on Memory System Performance (MSP 2002), June 2002.
18. A. Park and M. Farrens. Address Compression through Base Register Caching. in Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pages 193-199, November 1990.
19. K. Skadron, P.S. Ahuja. M. Martonosi. and D.W. Clark. Selecting a Single, Representative Sample for Accurate Simulation of SPECint Benchmarks. IEEE Transactions on Computers, 48(11); 1260-1281. November 1999.
20. P.P. Sotiriadis and A. Chandrakasan. Low Power Bus Coding Techniques Considering Inter-wire Capacitances. In Proceedings of Custom Integrated Circuits Conference:, pages 414-419, May 2000.
21. R. B. Tremaìne, P.A. Franaszek, J.T. Robinson, CO. Schulz, T.B. Smith, M.E. Wazlowski, and P.M. Bland. IBM Memory expansion Technology (MXT). IBM Journal of Research and Development, 45(2):27l-285, March 2001.
22. L. Villa. M. Yang, and K. Asanovic. Dynamic Zero Compression for Cache Energy Reduction. In Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, December 2000.
23. J.L. Wang and R.W. Quong. The Feasibility of Using Compression to Increase Memory System Performance. In Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems, January 1994.
24. Wayne Wolf. Computers as Components: Principles of Embed-ded Computing System Design. Morgan Kaufmann Publishers Inc., 2001.
25. A, Wolfe and A. Channin. Executing Compressed Programs on an Embedded RISC Architecture. In Proceedings of the Annual Symposium on Computer Architecture, pages 81-91, 1992.
26. J. Yang, Y. Zhang, and R. Gupta. Frequent Value Compression in Data Caches, In Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, November 2000.