Dynamic address compression schemes: A performance, energy, and cost study

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 458-463

  Liu, Jiangjiang ^a   Sundaresan, Krishnan ^b   Mahapatra, Nihar R ^b  

^a State University of New York   (United States)

^b Michigan State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUSBARS; COSTS; CROSSTALK; ENERGY DISSIPATION; ESTIMATION; MICROPROCESSOR CHIPS; TECHNOLOGY;

BUS ENERGY; ENERGY REDUCTION; FLOORPLANNING; ON-CHIP BUSES;

PACKET NETWORKS;

EID: 17644420768     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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