Area-efficient high-throughput MAP decoder architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 8, 2005, Pages 921-932

  Lee, Seok Jun ^a,b   Shanbhag, Naresh R ^a,c   Singer, Andrew C ^a,c,d,e,f  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c University of Illinois at Urbana Champaign   (United States)

^d Electrical and Computer Engineering Department   (United States)

^e MIT Educational Council   (United States)

^f Electrical and Computer Engineering Department ^*  (United States)

Author keywords

Area efficient; Block interleaved pipelining; High throughput; Parallel processing; Pipeline; Symbol based decoding; Turbo decoder; Turbo equalizer

Indexed keywords

AREA EFFICIENT; BLOCK-INTERLEAVED PIPELINING; HIGH THROUGHPUT; SYMBOL-BASED DECODING; TURBO DECODER; TURBO EQUALIZER;

BROADBAND NETWORKS; COMMUNICATION SYSTEMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER SIMULATION; ITERATIVE METHODS; PIPELINE PROCESSING SYSTEMS; TURBO CODES;

DECODING;

EID: 27144465561     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.853604     Document Type: Article

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