Design methodology for high-speed iterative decoder architectures

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 3, Issue , 2002, Pages

  Mansour, Mohammad M ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONVOLUTIONAL CODES; DECODING; ELECTRIC NETWORK ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MATHEMATICAL MODELS; OPTIMIZATION; TURBO CODES;

A POSTERIORI PROBABILITY; DECODING DELAY; FORWARD-BACKWARD RECURSION EQUATIONS; ITERATIVE DECODERS; PARALLEL-WINDOW ARCHITECTURE; RECURSION PATTERNS; RESOURCE TIME SCHEDULING; SOFT INPUT SOFT OUTPUT; TILE GRAPH;

VLSI CIRCUITS;

EID: 0141859005     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icassp.2002.5745301     Document Type: Conference Paper

References (9)

1. Near Shannon limit error-correcting coding and decoding: Turbo codes
2. Soft-input soft-output modules for the construction and distributed iterative decoding of code networks
3. Optimal decoding of linear codes for minimizing symbol error rate
4. A soft-input soft-output maximum a posteriori (MAP) module to decode parallel and serial concatenated codes
5. Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding
6. Energy efficient data transfer and storage organization for a MAP turbo decoder module
7. VLSI architectures for high-speed MAP decoders
8. A comparison of optimal and sub-optimal MAP decoding algorithms operatiting in the log domain
9. VLSI architectures for iterative decoders