-
1
-
-
0016037512
-
Optimal decoding of linear codes for minimizing symbol error rate
-
Mar
-
L. Bahl, J. Cocke. F. Jelinek, and J. Raviv. Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate. IEEE Tr. on Information Theory, IT-20:284-287, Mar. 1974.
-
(1974)
IEEE Tr. On Information Theory
, vol.IT-20
, pp. 284-287
-
-
Bahl, L.1
Cocke, J.2
Jelinek, F.3
Raviv, J.4
-
2
-
-
0033358167
-
Implementation aspects of turbo-decoders for future radio applications
-
Sept
-
F. Berens, A. Worm, H. Michel, and N. Wehn. Implementation Aspects of Turbo-Decoders for Future Radio Applications. In Proc. VTC’99 Fall, pages 2601-2605, Sept. 1999.
-
(1999)
Proc. VTC’99 Fall
, pp. 2601-2605
-
-
Berens, F.1
Worm, A.2
Michel, H.3
Wehn, N.4
-
3
-
-
0027297425
-
Near shannon limit error-correcting coding and decoding: Turbo-codes
-
Geneva, Switzerland, May
-
C. Berrou, A. Glavieux, and P. Thitimajshima. Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes. In Proc. ICC’93, pages 1064-1070, Geneva, Switzerland, May 1993.
-
(1993)
Proc. ICC’93
, pp. 1064-1070
-
-
Berrou, C.1
Glavieux, A.2
Thitimajshima, P.3
-
4
-
-
3042628793
-
-
PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany
-
H. Dawid. Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany, 1996.
-
(1996)
Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung
-
-
Dawid, H.1
-
5
-
-
85013616471
-
MAP channel decoding: Algorithm and VLSI architecture
-
IEEE
-
H. Dawid, G. Gehnen, and H. Meyr. MAP Channel Decoding: Algorithm and VLSI Architecture. In VLSI Signal Processing VI, pages 141-149. IEEE, 1993.
-
(1993)
VLSI Signal Processing VI
, pp. 141-149
-
-
Dawid, H.1
Gehnen, G.2
Meyr, H.3
-
6
-
-
84949796242
-
Low power implementation of a turbo-decoder on programmable architectures
-
Jan
-
F. Gilbert, A. Worm, and N. Wehn. Low Power Implementation of a Turbo-Decoder on Programmable Architectures. In Proc. ASP-DAC’01, Jan. 2001.
-
(2001)
Proc. ASP-DAC’01
-
-
Gilbert, F.1
Worm, A.2
Wehn, N.3
-
8
-
-
0000035405
-
Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding
-
March-April
-
P. Robertson, P. Höher, and E. Villebrun. Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding. ETT, 8(2):119-125, March-April 1997.
-
(1997)
ETT
, vol.8
, Issue.2
, pp. 119-125
-
-
Robertson, P.1
Höher, P.2
Villebrun, E.3
-
9
-
-
0033359191
-
Energy efficient data transfer and storage organization for a MAP turbo decoder module
-
Aug
-
C. Schurgers, M. Engels, and F. Catthoor. Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module. In Proc. ISLPED’99, pages 76-81, Aug. 1999.
-
(1999)
Proc. ISLPED’99
, pp. 76-81
-
-
Schurgers, C.1
Engels, M.2
Catthoor, F.3
-
10
-
-
0141859010
-
A 50 Mbit/s iterative turbo-decoder
-
Mar
-
F. Viglione et al. A 50 Mbit/s Iterative Turbo-Decoder. In Proc. DATE’00, pages 176-180, Mar. 2000.
-
(2000)
Proc. DATE’00
, pp. 176-180
-
-
Viglione, F.1
-
11
-
-
0033295960
-
Comparison of different turbo decoder realizations for IMT-2000
-
Deco
-
J. Vogt, K. Koora, A. Finger, and G. Fettweis. Comparison of Different Turbo Decoder Realizations for IMT-2000. In Proc. Globecom’99, pages 2704-2708, Dec. 1999.
-
(1999)
Proc. Globecom’99
, pp. 2704-2708
-
-
Vogt, J.1
Koora, K.2
Finger, A.3
Fettweis, G.4
-
13
-
-
0034515302
-
A high-speed MAP architecture with optimized memory size and power consumption
-
Oct
-
A. Worm, H. Lamm, and N. Wehn. A High-Speed MAP Architecture with Optimized Memory Size and Power Consumption. In Proc. SiPS 2000, pages 265-274, Oct. 2000.
-
(2000)
Proc. SiPS 2000
, pp. 265-274
-
-
Worm, A.1
Lamm, H.2
Wehn, N.3
|