Design of low-power high-speed maximum a priori decoder architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 258-265

  Worm, Alexander ^a   Lamm, Holger ^a   Wehn, Norbert ^a  

^a France   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION REQUIREMENTS; DATA-FLOW TRANSFORMATIONS; DECODER ARCHITECTURE; DESIGN SPACE EXPLORATION; INHERENT PARALLELISM; LOW-POWER CONSUMPTION; MAXIMUM A POSTERIORI DECODERS; REDUCED POWER CONSUMPTION;

EXHIBITIONS;

DESIGN;

EID: 9144248777     PISSN: 15301591     EISSN: None     Source Type: Journal    
DOI: 10.1109/DATE.2001.915035     Document Type: Article

References (13)

1. L. Bahl, J. Cocke. F. Jelinek, and J. Raviv. Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate. IEEE Tr. on Information Theory, IT-20:284-287, Mar. 1974.
2. F. Berens, A. Worm, H. Michel, and N. Wehn. Implementation Aspects of Turbo-Decoders for Future Radio Applications. In Proc. VTC’99 Fall, pages 2601-2605, Sept. 1999.
3. C. Berrou, A. Glavieux, and P. Thitimajshima. Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes. In Proc. ICC’93, pages 1064-1070, Geneva, Switzerland, May 1993.
4. H. Dawid. Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany, 1996.
5. H. Dawid, G. Gehnen, and H. Meyr. MAP Channel Decoding: Algorithm and VLSI Architecture. In VLSI Signal Processing VI, pages 141-149. IEEE, 1993.
6. F. Gilbert, A. Worm, and N. Wehn. Low Power Implementation of a Turbo-Decoder on Programmable Architectures. In Proc. ASP-DAC’01, Jan. 2001.
7. H. Michel and N. Wehn. Turbo-Decoder Quantization for UMTS. IEEE Communications Letters, 2001. Accepted.
8. P. Robertson, P. Höher, and E. Villebrun. Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding. ETT, 8(2):119-125, March-April 1997.
9. C. Schurgers, M. Engels, and F. Catthoor. Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module. In Proc. ISLPED’99, pages 76-81, Aug. 1999.
10. F. Viglione et al. A 50 Mbit/s Iterative Turbo-Decoder. In Proc. DATE’00, pages 176-180, Mar. 2000.
11. J. Vogt, K. Koora, A. Finger, and G. Fettweis. Comparison of Different Turbo Decoder Realizations for IMT-2000. In Proc. Globecom’99, pages 2704-2708, Dec. 1999.
12. A. Worm et al. Advanced Implementation Issues of Turbo-Decoders. In Proc. 2nd International Symposium on Turbo Codes and Related Topics, pages 351-354, Sept. 2000.
13. A. Worm, H. Lamm, and N. Wehn. A High-Speed MAP Architecture with Optimized Memory Size and Power Consumption. In Proc. SiPS 2000, pages 265-274, Oct. 2000.