Design of low-power high-speed maximum a priori decoder architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 258-265

  Worm, Alexander ^a   Lamm, Holger ^a   Wehn, Norbert ^a  

^a University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION REQUIREMENTS; DATA-FLOW TRANSFORMATIONS; DECODER ARCHITECTURE; DESIGN SPACE EXPLORATION; INHERENT PARALLELISM; LOW-POWER CONSUMPTION; MAXIMUM A POSTERIORI DECODERS; REDUCED POWER CONSUMPTION;

EXHIBITIONS;

DESIGN;

EID: 9144248777     PISSN: 15301591     EISSN: None     Source Type: Journal    
DOI: 10.1109/DATE.2001.915035     Document Type: Article

References (13)

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