A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo) codec

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Bougard, Bruno ^a,b   Giulietti, Alexandre ^a   Derudder, Veerle ^a   Weijers, Jan Willem ^a   Dupont, Steven ^a   Hollevoet, Lieven ^a   Catthoor, Francky ^b   Van Der Perre, Liesbet ^a   De Man, Hugo ^b   Lauwereins, Rudy ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; CHANNEL CAPACITY; CONVOLUTIONAL CODES; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT MANUFACTURE; ITERATIVE METHODS; OPTIMIZATION; PHASE LOCKED LOOPS; WIRELESS TELECOMMUNICATION SYSTEMS;

GAUSSIAN CHANNEL; WIRELESS BROADBAND COMMUNICATION;

TURBO CODES;

EID: 0037630984     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. C. Berrou et al., "Near Shannon Limit Error Correcting Coding and Decoding: Turbo-codes", IEEE International Conference on Communication, May 1993
2. M. Bickerstaff et al., "A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18mm CMOS", ISSCC Dig. Tech. Papers, vol. 45, pp. 124-125, Feb. 2002
3. M. Bekooij et al., "Power-efficient application-specific VLIW processor for turbo decoding", ISSCC Dig. Tech. Papers, vol. 44, pp. 180-181, Feb. 2001.
4. L.R. Bahl et al., "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate", IEEE Trans. on Information Theory, vol. 20, pp. 184-187, 1974
5. A. Giulietti et al., "Parallel Turbo Code Interleavers: Avoiding Collisions in Accesses to Storage Elements", Electronics Letters, vol. 38 No. 5, pg. 132-134, Feb. 2002
6. F. Catthoor et al., "Custom Memory Management Methodology, Exploration of Memory Organization for Embedded Multimedia System Design", Kluwer Academic Publishers, 1998