High-performance programmable SISO decoder VLSI implementation for decoding turbo codes

Conference Record / IEEE Global Telecommunications Conference

Volumn 1, Issue , 2001, Pages 305-309

  Miyauchi, Toshiyuki ^a   Yamamoto, Kouhei ^a   Yokokawa, Takashi ^a   Kan, Makiko ^a   Mizutani, Yuichi ^a   Hattori, Masayuki ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; FREQUENCIES; PHASE SHIFT KEYING; TURBO CODES; VLSI CIRCUITS;

SOFT-IN SOFT-OUT (SISO) DECODERS;

DECODING;

EID: 0035687581     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Near shannon limit error-correcting coding and decoding: Turbo-codes
2. Characteristics of a sixteen-state Turbo-encoder/decoder(Turbo4)
3. Implementation and performance of a Turbo/MAP decoder
4. DSP implementation of the newly proposed CCSDS telemetry channel coding standard
5. Efficient turbo decoder design and its implementation on a low-cost, 16-bit fixed-point DSP
6. Optimal decoding of linear codes for minim/zing symbol error rate
7. Soft-output decoding algorithms for continuous decoding of parallel concatenated convolutional codes
8. Efficient implementation of continuous MAP decoders and a synchronisation technique for turbo decoders
9. An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes
10. Stanford telecom VLSI design of a convolutional decoder
11. A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain
12. Telemetry channel coding
13. Serial concatenation of interleaved codes: Performance analysis, design and iterative decoding
14. Bandwidth-efficient turbo trellis-coded modulation using punctured component codes
15. Serial concatenated trellis coded modulation with rate-1 inner code