A high speed architecture for MAP decoder

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2002-January, Issue , 2002, Pages 69-74

  El Assal, M ^a   Bayoumi, M ^a  

^a Informatics Research Institute   (United States)

Author keywords

Computer architecture; Delay; Error correction codes; Field programmable gate arrays; Iterative algorithms; Iterative decoding; Maximum likelihood decoding; Probability; Prototypes; Throughput

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE METHODS; MAXIMUM LIKELIHOOD; MEMORY ARCHITECTURE; PROBABILITY; SIGNAL PROCESSING; THROUGHPUT;

DELAY; ERROR CORRECTION CODES; ITERATIVE ALGORITHM; MAXIMUM LIKELIHOOD DECODING; PROTOTYPES;

ITERATIVE DECODING;

EID: 27144522760     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2002.1049687     Document Type: Conference Paper

References (7)

1. L. R. Bahl, J. Cocke, F. Jelinek, and J. Rajiv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. ?, no. 3, pp. 284-287, March 1974.
2. Lin-Nan Lee, A. Roger Hammons, Jr. Feng-Wen Sun, and Mustafa Eroz, "Application and standardization of turbo codes in third-generation high-speed wireless data services," IEEE Trans. on Vehicular Technology, vol. 49, no. 6, pp. 2198-2206, Nov. 2000.
3. P. Robertson E. Villebrun and P. Hoeher, "A comparison of optimal and sub-optimal map decoding algorithms operating in the log domain," in Proc. International Conference on Communications ICC, June 1995, p. 10091013.
4. Andrew J. Viterbi, "An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes," IEEE Transactions on Selected Areas In Communications, vol. 16, no. 2, pp. 260-264, February 1998.
5. Curt Schurgers, Francky Catthoor, and Marc Engels, "Memory optimization of MAP turbo decoder algorithms," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, pp. 305-312, April 2001.
6. Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, and Maurizio Zamboni, "VLSI architectures for turbo codes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 3, pp. 369-379, September 1999.
7. Engling Yeo, Payam Pakzad, Borivoje Nikolic, and Venkat Anantharam, "VLSI architectures for turbo codes," IEEE Transactions on Magnetics, vol. 37, no. 2, pp. 748-755, March 2001.