-
1
-
-
0029516230
-
EEPROM/Flash sub-3.0 V drain-source bias hot carrier writing
-
J. D. Bude, A. Frommer, M. R. Pinto, and G. R. Weber, "EEPROM/Flash sub-3.0 V drain-source bias hot carrier writing," in IEDM Tech. Dig., 1995, pp. 989-991.
-
IEDM Tech. Dig., 1995
, pp. 989-991
-
-
Bude, J.D.1
Frommer, A.2
Pinto, M.R.3
Weber, G.R.4
-
2
-
-
84886448125
-
Secondary electron Flash - A high performance low power Flash technology for 0.35 μm and below
-
J. D. Bude et al., "Secondary electron Flash - A high performance low power Flash technology for 0.35 μm and below," in IEDM Tech. Dig., 1997, pp. 279-282.
-
IEDM Tech. Dig., 1997
, pp. 279-282
-
-
Bude, J.D.1
-
3
-
-
0033190189
-
Low voltage Flash memory by use of a substrate bias
-
M. Mastrapasqua, "Low voltage Flash memory by use of a substrate bias," Microelectron. Eng., vol. 48, pp. 389-394, 1999.
-
(1999)
Microelectron. Eng.
, vol.48
, pp. 389-394
-
-
Mastrapasqua, M.1
-
4
-
-
0032738943
-
A new and flexible scheme for hot-electron programming of nonvolatile memory cells
-
Jan.
-
D. Esseni, A. Della Strada, P. Cappelletti, and B. Ricco, "A new and flexible scheme for hot-electron programming of nonvolatile memory cells," IEEE Trans. Electron Devices, vol. 46, pp. 125-133, Jan. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 125-133
-
-
Esseni, D.1
Della Strada, A.2
Cappelletti, P.3
Ricco, B.4
-
5
-
-
0036638639
-
CHISEL Flash EEPROM - Part-1: Performance and scaling
-
July
-
S. Mahapatra, S. Shukuri, and J. D. Bude, "CHISEL Flash EEPROM - Part-1: Performance and scaling," IEEE Trans. Electron Devices, vol. 49, pp. 1296-1301, July 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 1296-1301
-
-
Mahapatra, S.1
Shukuri, S.2
Bude, J.D.3
-
6
-
-
0029481650
-
Gate current by impact ionization feedback in sub-micron MOSFET technologies
-
J. D. Bude, "Gate current by impact ionization feedback in sub-micron MOSFET technologies," in Proc. Symp. VLSI Technology, 1995, pp. 101-102.
-
Proc. Symp. VLSI Technology, 1995
, pp. 101-102
-
-
Bude, J.D.1
-
7
-
-
0033079587
-
A better understanding of substrate enhanced gate current in MOSFETs and Flash cells - Part I: Phenomenological aspects
-
Feb.
-
D. Esseni and L. Selmi, "A better understanding of substrate enhanced gate current in MOSFETs and Flash cells - Part I: Phenomenological aspects," IEEE Trans. Electron Devices, vol. 46, pp. 369-375, Feb. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 369-375
-
-
Esseni, D.1
Selmi, L.2
-
8
-
-
0033079579
-
A better understanding of substrate enhanced gate current in MOSFETs and Flash cells - Part II: Physical analysis
-
Feb.
-
L. Selmi and D. Esseni, "A better understanding of substrate enhanced gate current in MOSFETs and Flash cells - Part II: Physical analysis," IEEE Trans. Electron Devices, vol. 46, pp. 376-382, Feb. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 376-382
-
-
Selmi, L.1
Esseni, D.2
-
9
-
-
0034297544
-
Monte Carlo simulation of CHISEL Flash memory cell
-
Oct.
-
J. D. Bude, M. R. Pinto, and R. K. Smith, "Monte Carlo simulation of CHISEL Flash memory cell," IEEE Trans. Electron Devices, vol. 47, pp. 1873-1881, Oct. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 1873-1881
-
-
Bude, J.D.1
Pinto, M.2
Smith, R.K.3
-
10
-
-
0004038844
-
-
Boston, MA: Kluwer Acad. Publishers
-
P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston, MA: Kluwer Acad. Publishers, 1999.
-
(1999)
Flash Memories
-
-
Cappelletti, P.1
Golla, C.2
Olivo, P.3
Zanoni, E.4
-
11
-
-
0029403785
-
A convergence scheme for over erased Flash EEPROMs using substrate enhanced hot electron injection
-
Sept.
-
C. Y. Hu et al., "A convergence scheme for over erased Flash EEPROMs using substrate enhanced hot electron injection," IEEE Electron Device Lett., vol. 11, pp. 500-502, Sept. 1995.
-
(1995)
IEEE Electron Device Lett.
, vol.11
, pp. 500-502
-
-
Hu, C.Y.1
-
12
-
-
0029516372
-
Substrate-current-induced hot electron (SCIHE) injection: A new convergence scheme for Flash memory
-
C. Y. Hu et al., "Substrate-current-induced hot electron (SCIHE) injection: A new convergence scheme for Flash memory," in IEDM Tech. Dig., 1995, pp. 283-286.
-
IEDM Tech. Dig., 1995
, pp. 283-286
-
-
Hu, C.Y.1
-
13
-
-
33749938628
-
Comparison of current Flash EEPROM erasing methods: Stability and how to control
-
K. Yoshikawa et al., "Comparison of current Flash EEPROM erasing methods: Stability and how to control," in IEDM Tech. Dig., 1992, pp. 595-598.
-
IEDM Tech. Dig., 1992
, pp. 595-598
-
-
Yoshikawa, K.1
-
14
-
-
0036637851
-
CHISEL Flash EEPROM - Part 2: Reliability
-
July
-
S. Mahapatra, S. Shukuri, and J. D. Bude, "CHISEL Flash EEPROM - Part 2: Reliability," IEEE Trans. Electron Devices, vol. 49, pp. 1302-1307, July 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 1302-1307
-
-
Mahapatra, S.1
Shukuri, S.2
Bude, J.D.3
-
15
-
-
0034315571
-
Injection efficiency of CHISEL gate currents in short MOS devices: Physical mechanisms, device implications and sensitivity to technological parameters
-
Nov.
-
D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, "Injection efficiency of CHISEL gate currents in short MOS devices: Physical mechanisms, device implications and sensitivity to technological parameters," IEEE Trans. Electron Devices, vol. 47, pp. 2194-2200, Nov. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 2194-2200
-
-
Esseni, D.1
Selmi, L.2
Ghetti, A.3
Sangiorgi, E.4
-
16
-
-
0033347823
-
The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and Flash memory cells
-
____, "The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and Flash memory cells," in IEDM Tech. Dig., 1999, pp. 275-279.
-
IEDM Tech. Dig., 1999
, pp. 275-279
-
-
Esseni, D.1
Selmi, L.2
Ghetti, A.3
Sangiorgi, E.4
-
17
-
-
84954185679
-
A self-convergence erasing scheme for a simple stacked gate Flash EEPROM
-
S. Yamada et al., "A self-convergence erasing scheme for a simple stacked gate Flash EEPROM," in IEDM Tech. Dig., 1991, pp. 307-310.
-
IEDM Tech. Dig., 1991
, pp. 307-310
-
-
Yamada, S.1
-
18
-
-
0027206273
-
Rigorous theory and simplified model of the band-to-band tunneling in silicon
-
A. Schenk, "Rigorous theory and simplified model of the band-to-band tunneling in silicon," in Solid-State Electron., vol. 36, 1993, pp. 19-34.
-
(1993)
Solid-State Electron.
, vol.36
, pp. 19-34
-
-
Schenk, A.1
-
19
-
-
0026955196
-
Analysis of the subthreshold slope and linear transconductance techniques for the extraction of the capacitance coupling coefficients of floating-gate devices
-
Nov.
-
M. Wong, D. K.-Y. Liu, and S. S.-W. Huang, "Analysis of the subthreshold slope and linear transconductance techniques for the extraction of the capacitance coupling coefficients of floating-gate devices," IEEE Electron Device Lett., vol. 13, pp. 566-568, Nov. 1992.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 566-568
-
-
Wong, M.1
Liu, D.K.-Y.2
Huang, S.S.-W.3
-
20
-
-
0142009676
-
CHISEL programming operation of scaled NOR Flash EEPROM-ROMs - Effect of voltage scaling, device scaling and technological parameters
-
Oct.
-
N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao, S. Shukuri, and J. D. Bude, "CHISEL programming operation of scaled NOR Flash EEPROM-ROMs - Effect of voltage scaling, device scaling and technological parameters," IEEE Trans. Electron Devices, vol. 50, pp. 2104-2111, Oct. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 2104-2111
-
-
Mohapatra, N.R.1
Nair, D.R.2
Mahapatra, S.3
Rao, V.R.4
Shukuri, S.5
Bude, J.D.6
|