Comparison of current flash EEPROM erasing methods: Stability and how to control

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 595-598

  Yoshikawa, K ^a   Yamada, S ^a   Miyamoto, J ^a   Suzuki, T ^a   Oshikiri, M ^a   Obi, E ^a   Hiura, Y ^a   Yamada, K ^a   Ohshima, Y ^a   Atsumi, S ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELDS; ELECTRON DEVICES; THRESHOLD VOLTAGE;

CELL PARAMETER; DEVICE PARAMETER FLUCTUATIONS; EFFECTIVE TOOL; ELECTRIC FIELD FLUCTUATIONS; FLASH DEVICES; FLASH EEPROMS; NEGATIVE GATE; THRESHOLD VOLTAGE DISTRIBUTION;

ELECTRIC GROUNDING;

EID: 33749938628     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307431     Document Type: Conference Paper

References (6)

1. V. N. Kynett et. al. "h in-system npogrammable 256k CMOS Flash memory" ISSCC Digest of Technical Papers. 1988, p. 132.
2. S. Tam, et. al., "A high density CMOS 1-T electrically erasable nonvolatile (Flash) memory technology", Symp. on VLSI Technology Dig. Tech. Papers, 1988, p. 31.
3. N. Ajika. M. Ohi. H. Arima, T. Matsukawa and N. Tsubouchi, "A 5V only 16M bit Flash EEPROM cell with a simple stacked gate structure, " IEDM Tech. Dig., 1990. p. 115.
4. N. Kodama. K. Saitoh, H. Shirai, T. Okazawa and Y. Hokari. "A 5V only 16Mbit Hash EEPROM cell using highly reliable write/erase technology". Sym. on VLSI Technology Dig. Tech. Papers, 1991, p. 75.
5. S. Yamada, et. al. "A self-convergence erase scheme for a simple stacked gate Hash EEPROM. 1991, p. 307.
6. M. Kuriyama et al "A 5V only 0.-Flash EEPROM with row decoder scheme in triple-well structure", ISSCC Digest of Technical Papers, 1992. p. 153.