Strategies for nanoelectronics

Microelectronic Engineering

Volumn 81, Issue 2-4, 2005, Pages 405-419

  Cerofolini, G F ^a   Arena, G ^a   Camalleri, M ^a   Galati, C ^a   Reina, S ^a   Renna, L ^a   Mascolo, D ^a   Nosik, V ^b  

^a STMICROELECTRONICS   (Italy)

^b STMICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANISOTROPY; ARRAYS; INTEGRATED CIRCUITS; MOS DEVICES; MOSFET DEVICES; SILICA;

FILM THICKNESS; GATE DIELECTRICS; NANOELECTRONICS; SINGLE ELECTRON TUNNELING;

NANOTECHNOLOGY;

EID: 23444457964     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.03.041     Document Type: Conference Paper

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