Understanding the impact of inter-thread cache interference on ILP in modern SMT processors

Journal of Instruction-Level Parallelism

Volumn 7, Issue , 2005, Pages

  Kihm, Joshua ^a   Settle, Alex ^a   Janiszewski, Andrew ^a   Connors, Dan ^a  

^a University of Colorado at Boulder   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ON-CHIP PARALLELISM; SIMULTANEOUS MULTITHREADING (SMT); SUPER-SCALAR PROCESSORS; WORKLOADS;

CACHE MEMORY; COMPUTER HARDWARE; DECISION MAKING; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; RESOURCE ALLOCATION; SCHEDULING; THROUGHPUT;

MICROPROCESSOR CHIPS;

EID: 21244486659     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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