Implementation of fine-grained cache monitoring for improved SMT scheduling

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 326-331

  Kihm, Joshua L ^a   Connors, Daniel A ^a  

^a UCB 450   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MONITORING; HARDWARE CONSTRAINTS; MULTITHREADED ARCHITECTURE; RUN-TIME SCHEDULING;

ALGORITHMS; COMPUTER ARCHITECTURE; COST EFFECTIVENESS; INFORMATION ANALYSIS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SCHEDULING;

CACHE MEMORY;

EID: 17644383033     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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