Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 110-116

  Cheek, Betsy J ^a   Stutzke, Nate ^b   Kumar, Santosh ^c   Baker, R Jacob ^a   Moll, Amy J ^a   Knowlton, William B ^a  

^a Boise State University   (United States)

^b UNIVERSITY OF COLORADO   (United States)

^c C M Innovations   (United States)

Author keywords

Circuit model; Circuit reliability; CMOS; Dielectric breakdown; Gate oxide reliability; Inverter degradation; MOSFEET degradation

Indexed keywords

CIRCUIT SIMULATION; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; DEGRADATION; DELAY CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; GATE DIELECTRICS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; RELIABILITY; THRESHOLD VOLTAGE;

CIRCUIT MODELING; CIRCUIT RELIABILITY; GATE OXIDE DEGRADATION; GATE OXIDE RELIABILITY; OFF-STATE LEAKAGE CURRENT; PERFORMANCE DEGRADATION; RAMPED VOLTAGE STRESS; VOLTAGE TRANSFER CURVES;

TIMING CIRCUITS;

EID: 11144226292     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315309     Document Type: Conference Paper

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