SCOPUS 정보 검색 플랫폼

Volumn 19, Issue 5, 2002, Pages 65-73

Extending OPMISR beyond 10× scan test efficiency

(9) Barnhart, Carl c Brunkhorst, Vanessa c Distler, Frank c Farnsworth, Owen c Ferko, Andrew c Keller, Brion b Scott, David c Koenemann, Bernd c Onodera, Takeshi a

a SONY CORPORATION (Japan)

b IBM MICROELECTRONICS (United States)

c NONE

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DATA COMPRESSION; DESIGN FOR TESTABILITY; ELECTRONICS INDUSTRY; FAILURE ANALYSIS; INSPECTION; LOGIC DESIGN; SOFTWARE ENGINEERING;

AUTOMATIC TEST PATTERN GENERATOR; DATA VOLUME; ON-PRODUCT MULTIPLE-INPUT SIGNATURE REGISTER; RUN LENGTH ENCODING; SCAN TEST TIME; TEST DATA SUPPLY; WEIGHTED RANDOM PATTERN TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0036734162 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/MDT.2002.1033794 Document Type: Article

Times cited : (105)

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5
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.