Synthesis of single-output space compactors for scan-based sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 10, 2002, Pages 1171-1179

  Bhattacharya, Bhargab B ^a,b   Dmitriev, Alexej ^c   Gössel, Michael ^c   Chakrabarty, Krishnendu ^a,d  

^a IEEE   (India)

^b INDIAN STATISTICAL INSTITUTE   (India)

^c UNIVERSITY OF POTSDAM   (Germany)

^d Duke University   (United States)

Author keywords

Scan based sequential circuits; Space compaction; Testing

Indexed keywords

CIRCUIT UNDER TEST; SCAN-BASED SEQUENTIAL CIRCUITS; SPACE COMPACTORS; ZERO ALIASING;

ELECTRIC NETWORK SYNTHESIS; ERRORS; FUNCTIONS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; THEOREM PROVING;

SEQUENTIAL CIRCUITS;

EID: 0036811327     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.802275     Document Type: Article

References (21)

1. Y. Zorian, E. J. Marinissen, and S. Dey, "Testing embedded core based system chips," in Proc. Int. Test Conf., 1998, pp. 130-143.
2. M Gössel, E. Sogomonyan, and A. Morosov, "A new totally error propagating compactor for arbitrary cores with digital interfaces," in Proc. VTS, 1999, pp. 49-56.
3. B. Pouya and N. A. Touba, "Synthesis of zero-aliasing elementary-tree space compactors," in Proc. VTS, 1998, pp. 70-77.
4. M. Seuring, and M. Gössel, and E. Sogomonyan, "A structural approach for space compaction for concurrent checking and BIST," in Proc. VTS, 1998, pp. 354-361.
5. K. Chakrabarty and J. P. Hayes, "Test response compaction using multiplexed parity trees," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1399-1408, Nov. 1996.
6. K. Chakrabarty, "Zero-aliasing space compaction using linear compactors with bounded overhead," IEEE Trans. Computer-Aided Design, vol. 17, pp. 452-457, May 1998.
7. K. Chakrabarty, B. T. Murray, and J. P. Hayes, "Optimal zero-aliasing space compaction of test responses," IEEE Trans. Comput., vol. 47, pp. 1171-1187, Nov. 1998.
8. M. Seuring and K. Chakrabarty, "Space compaction of test responses for IP cores using orthogonal transmission functions," in Proc. VTS, 2000, pp. 213-219
9. J. Savir, "On shrinking wide compressors," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1379-1387, 1995.
10. S. M. Reddy, K. K. Saluja, and M. G. Karpovsky, "A data compression technique for built-in self-test," IEEE Trans. Comput., vol. C-37, pp. 1151-1165, Sept. 1988.
11. Y. Zorian and V. K. Agarwal, "Optimizing error masking in BIST by output data modification," J Electron. Testing: Theory Applicat., vol. 1, pp. 59-71, 1990.
12. B. B. Bhattacharya, A. Dmitriev, and M. Gössel, "Zero aliasing space compaction using a single periodic output and its application to testing of embedded cores," in Proc. Int. Conf. VLSI Design, 2000, pp. 382-387.
13. G. Hetheringten, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, "Logic BIST for large industrial designs," in Proc. Int. Test Conf., 1999, pp. 358-367.
14. H. Lang, J. Pfeiffer, and J. Maguire, "Using on-chip test pattern compression for full scan SoC designs," in Proc. ETW, 2000, pp. 47-52.
15. S. Kundu, E. S. Sogomonyan, M. Gössel, and S. Tarnick, "Self-checking comparator with one periodic output," IEEE Trans. Comput., vol. 45, pp. 379-380, Mar. 1996.
16. R. K. Brayton, G. D. Harchel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer, 1984.
17. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, A. Saldanha, H. Savoj, P. R. Stephan, and A. L. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis," Electronic Res. Lab., Tech. Rep. UCB/ERL M92/41, 1992.
18. I. Hamzaoglu, and J. H. Patel, "Test set compaction algorithm for combinational circuits," in Proc. ICCAD, Nov. 1998, MINTEST-[Online]. Available:http://www.crhc.uiuc.edu/IGATE, pp. 283-289.
19. M. C. Hansen and J. P. Hayes, "High-level test generation using physically-induced faults," in Proc. VTS, 1995, pp. 20-28.
20. J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems. Englewood Cliffs, NJ: Prectine Hall, 1998, pp. 49-50.
21. J. Aerts and E. J. Marinissen, "Scan chain design for test time reduction in core-based IC's," in Proc. Int. Test Conf., 1998, pp. 448-457.