VLSI architectural design tradeoffs for sliding-window Log-MAP decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 4, 2005, Pages 439-447

  Wu, Chien Ming ^a   Shieh, Ming Der ^b   Wu, Chien Hsing ^c   Hwang, Yin Tsung ^d   Chen, Jun Hong ^b  

^a NATIONAL APPLIED RESEARCH LABORATORIES   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^d NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

Iterative decoding; MAP algorithm; Sliding window algorithm; Turbo code; VLSI architecture and design

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DECODING; ERROR CORRECTION; REAL TIME SYSTEMS;

ITERATIVE DECODING; MAP ALGORITHM; SLIDING WINDOW ALGORITHMS; TURBO CODE; VLSI ARCHITECTURE AND DESIGNS;

VLSI CIRCUITS;

EID: 16444366501     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842917     Document Type: Article

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