Block processing technique for low power turbo decoder design

IEEE Vehicular Technology Conference

Volumn 2, Issue , 2002, Pages 1025-1029

  Lee, Inkyu ^a   Vallejo, Marisa Lopez ^b   Mujtaba, Syed Aon ^a  

^a AGERE SYSTEMS   (United States)

^b UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; TURBO CODES; VERY LONG INSTRUCTION WORD ARCHITECTURE;

BLOCK PROCESSING; LOW POWER TURBO DECODER DESIGN;

DECODING;

EID: 0036349039     PISSN: 07400551     EISSN: None     Source Type: Journal    
DOI: 10.1109/VTC.2002.1002644     Document Type: Article

References (10)

1. Near Shannon limit error-correcting coding and decoding: Turbo-codes
2. Energy efficient data transfer and storage organization for a MAP turbo decoder module
3. Power minimization by optimizing data-transfers in turbo-decoders
4. Vlsi implementation issues of turbo decoder design for wireless communications
5. A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain
6. Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck
7. A block processing method for designing high-speed Viterbi detectors
8. Modification of the MAP algorithm for memory savings
9. An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes