Memory arrangements in turbo decoders using sliding-window BCJR algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Wu, Chien Ming ^a   Shieh, Ming Der ^a   Wu, Chien Hsing ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; PROGRAM PROCESSORS; SIGNAL TO NOISE RATIO;

MEMORY ARRANGEMENT; SOFT OUTPUT VITERBI ALGORITHM; TURBO CODING; TURBO DECODERS;

TURBO CODES;

EID: 0036287911     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Near Shannon limit error-correcting coding and decoding: Turbo-codes
2. Optimal decoding of linear codes for minimizing symbol error rate
3. Analysis, design, and iterative decoding of double serially concatenated codes with interleavers
4. A parallel decoding scheme for turbo codes
5. Soft-output decoding algorithms in iterative decoding of turbo-codes
6. Generalized trace back techniques for survivor memory management in the Viterbi algorithm
7. Memory optimization of MAP turbo decoder algorithms
8. VLSI architectures for turbo codes
9. An intuitive justification of the MAP decoder for convolutional codes
10. VLSI implementation considerations for turbo decoding using a low latency log-MAP