A 80 Mb/s low-power scalable turbo codec core

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 389-392

  Giulietti, Alexandre ^a   Bougard, Bruno ^a   Derudder, Veerle ^a   Dupont, Steven ^a   Weijers, Jan Willem ^a   Van der Perre, Liesbet ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; BROADBAND NETWORKS; C (PROGRAMMING LANGUAGE); CODE CONVERTERS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; CONVOLUTIONAL CODES; DATA FLOW ANALYSIS; DECODING; ENCODING (SYMBOLS); OPTIMIZATION; PHASE SHIFT KEYING; STATIC RANDOM ACCESS STORAGE;

HIGH-SPEED TURBO CODECS; LOW-POWER SCALABLE TURBO CODEC CORES;

TURBO CODES;

EID: 0036053036     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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