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Volumn , Issue , 1999, Pages 182-183
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VLSI implementation considerations for turbo decoding using a low latency log-MAP
a a |
Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
BIT ERROR RATE;
COMPUTATIONAL COMPLEXITY;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
COMPUTER SIMULATION;
PROBABILITY;
SIGNAL TO NOISE RATIO;
VLSI CIRCUITS;
LOG MAXIMUM APOSTERIOR PROBABILITY ALGORITHM;
TURBO DECODING;
DECODING;
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EID: 0033329774
PISSN: 0747668X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/icce.1999.785223 Document Type: Conference Paper |
Times cited : (6)
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References (9)
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