Automatic test pattern generation for resistive bridging faults

Proceedings - Ninth IEEE European Test Symposium, ETS 2004

Volumn , Issue , 2004, Pages 160-165

  Engelke, Piet ^a   Polian, Ilia ^a   Renovell, Michel ^b   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b LIRMM   (France)

Author keywords

ATPG; Bridging faults; Resistive short defects; SAT

Indexed keywords

AUTOMATIC TEST PATTERN GENERATOR (ATPG); BRIDGING FAULTS; RESISTIVE SHORT DEFECTS; SAT;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); VECTORS;

ELECTRIC FAULT CURRENTS;

EID: 15844365177     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETSYM.2004.1347652     Document Type: Conference Paper

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