Precise test generation for resistive bridging faults of CMOS combinational circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 510-519

  Maeda, Toshiyuki ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; GATES (TRANSISTOR); HEURISTIC METHODS; INTEGRATED CIRCUIT TESTING; THRESHOLD VOLTAGE; VLSI CIRCUITS;

LOGIC TESTING METHOD; RESISTIVE BRIDGING FAULT; STUCK AT FAULT MODEL; TEST GENERATION;

CMOS INTEGRATED CIRCUITS;

EID: 0034478411     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)