A Circuit Level Fault Model for Resistive Bridges

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 4, 2003, Pages 546-559

  Li, Z ^a   Lu, X ^a   Qiu, W ^a   Shi, W ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Bridge faults; Delay faults; Fault models

Indexed keywords

COMPUTER SIMULATION; ELECTRIC MEASURING BRIDGES; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS; SEMICONDUCTOR DEVICE TESTING;

DELAY FAULTS;

DELAY CIRCUITS;

EID: 0142063548     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/944027.944036     Document Type: Article

References (17)

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