Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 767-775

  Liao, Yuyun ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGE CIRCUITS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; OPTIMIZATION;

BRIDGING FAULTS; GATE SENSITIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0030402883     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (34)