The pros and cons of very-low-voltage testing: An analysis based on resistive bridging faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 171-178

  Engelke, Piet ^a   Polian, Ilia ^a   Renovell, Michel ^b   Seshadri, Bharath ^c   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b LIRMM   (France)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Resistive short defects; Very Low Voltage testing

Indexed keywords

ANALOGUE DETECTABILITY INTERVAL (ADI); RESISTIVE BRIDGING FAULTS; RESISTIVE SHORT DEFECTS; VERY-LOW-VOLTAGE TESTING;

COMPUTER SIMULATION; COST EFFECTIVENESS; ELECTRIC CONDUCTIVITY; ELECTRIC FAULT CURRENTS; ELECTRIC POWER SYSTEMS; INTEGRATED CIRCUITS; PROBABILITY;

ELECTRIC POTENTIAL;

EID: 3142723471     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299240     Document Type: Conference Paper

References (17)

1. H. Hao and E.J. McCluskey. Very-Low-Voltage testing for weak CMOS logic ICs. In Int'l Test Conf., pages 275-284, 1993.
2. M.H. Woods. MOS VLSI reliability and yield trends. Proc. of the IEEE, 74(12):1715-1729, 1986.
3. M. Renovell, P. Hue, and Y. Bertrand. CMOS bridge fault modeling. In VLSI Test Symp., pages 392-397, 1994.
4. M. Renovell, P. Hue, and Y. Bertrand. The concept of resistance interval: A new parametric model for resistive bridging fault. In VLSI Test Symp., pages 184-189, 1995.
5. M. Renovell, F. Azaïs, and Y. Bertrand. Detection of defects using fault model oriented test sequences. Jour. of Electronic Testing: Theory and Applications, 14:13-22, 1999.
6. V. Sar-Dessai and D.M.H. Walker. Accurate fault modeling and fault simulation of resistive bridges. In Int. Symp. Defect and Fault Tolerance in VLSI Systems, pages 102-107, 1998.
7. V. Sar-Dessai and D.M.H. Walker. Resistive Bridge Fault Modeling, Simulation and Test Generation. In Int'l Test Conf., pages 596-605, 1999.
8. C. Lee and D. M. H. Walker. PROBE: A PPSFP simulator for resistive bridging faults. In VLSI Test Symp., pages 105-110, 2000.
9. P. Engelke, I. Polian, M. Renovell, and B. Becker. Simulating resistive bridging and smck-at faults. In Int'l Test Conf., pages 1051-1059, 2003.
10. Y. Liao and D.M.H. Walker. Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages. In Int'l Test Conf, pages 767-775, 1996.
11. M. Renovell, P. Hue, and Y. Bertrand. Bridging fault coverage improvement by power supply control. In VLSI Test Symp., pages 338-343, 1996.
12. S. Ma, I. Shaik, and R. Scott-Fetherston. A comparison of bridging fault simulation methods. In Int'l Test Conf, pages 587-595, 1999.
13. R. Rodríguez-Montañés, E.M.J.G. Bruls, and J. Figueras. Bridging defects resistance measurements in a CMOS process. In Int'l Test Conf., pages 892-899, 1992.
14. I. Polian, P. Engelke, M. Renovell, and B. Becker. Modelling feedback bridging faults with non-zero resistance. In European Test Workshop, 2003.
15. B.R. Benware, R. Madge, C. Lu, and R. Daasch. Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs. In VLSI Test Symp., pages 39-46, 2003.
16. B. Krusemann and S. van den Oetelaar. Detection of resistive shorts in deep sub-micron technologies. In Int'l Test Conf., pages 866-875, 2003.
17. Z. Li, X. Lu, W. Qiu, W. Shi, and D.M.H. Walker. A circuit level fault model for resistive bridges. ACM Trans. on Design Automation of Electronic Systems, 8(4):546-559, 10 2003.