메뉴 건너뛰기




Volumn 47, Issue 1, 2003, Pages 99-106

Analysis of the anomalous drain current characteristics of halo MOSFETs

Author keywords

Drain current modeling; Halo structure; MOSFET; Subthreshold; Threshold voltage

Indexed keywords

CHARGE TRANSFER; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FIELD EFFECTS; THRESHOLD VOLTAGE;

EID: 0037211010     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00268-X     Document Type: Article
Times cited : (8)

References (17)
  • 1
    • 33646900503 scopus 로고    scopus 로고
    • Device scaling limits of Si MOSFETs and their application dependencies
    • Frank D.J., Dennard R.H., Nowak E., Solomon P.M., Taur Y., Wong H.P. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE. 89(3):2001;259-283.
    • (2001) Proc. IEEE , vol.89 , Issue.3 , pp. 259-283
    • Frank, D.J.1    Dennard, R.H.2    Nowak, E.3    Solomon, P.M.4    Taur, Y.5    Wong, H.P.6
  • 2
    • 0033100138 scopus 로고    scopus 로고
    • CMOS technology-year 2010 and beyond
    • Iwai H. CMOS technology-year 2010 and beyond. IEEE J. Solid-State Circ. 34(3):1999;357-366.
    • (1999) IEEE J. Solid-State Circ. , vol.34 , Issue.3 , pp. 357-366
    • Iwai, H.1
  • 3
    • 0033325337 scopus 로고    scopus 로고
    • Modeling of pocket implanted MOSFETs for anomalous analog behavior
    • Cao K.M., Liu W., Jin X., Green K., Krick J., Vrotsos T.et al. Modeling of pocket implanted MOSFETs for anomalous analog behavior. IEDM Tech. Dig. 1:1999;171-174.
    • (1999) IEDM Tech. Dig. , vol.1 , pp. 171-174
    • Cao, K.M.1    Liu, W.2    Jin, X.3    Green, K.4    Krick, J.5    Vrotsos, T.6
  • 6
    • 0035446264 scopus 로고    scopus 로고
    • Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain n-MOSFETs
    • Miura N., Abe Y., Sugihara K., Oishi T., Furukawa T., Nakahata T.et al. Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain n-MOSFETs. IEEE Trans. Electron Dev. 48(9):2001;1969-1974.
    • (2001) IEEE Trans. Electron Dev. , vol.48 , Issue.9 , pp. 1969-1974
    • Miura, N.1    Abe, Y.2    Sugihara, K.3    Oishi, T.4    Furukawa, T.5    Nakahata, T.6
  • 8
    • 0030381962 scopus 로고    scopus 로고
    • Degradation of MOSFETs drive current due to halo ion implantation
    • Hwang H., Lee D.H., Hwang J.M. Degradation of MOSFETs drive current due to halo ion implantation. Int. Electron Dev. Meet. 1996;567-570.
    • (1996) Int. Electron Dev. Meet. , pp. 567-570
    • Hwang, H.1    Lee, D.H.2    Hwang, J.M.3
  • 9
    • 0029357172 scopus 로고
    • Computation of current and transconductance of a nonuniformly doped channel MOSFET with ac arbitrary doping profile
    • Wang C.L. Computation of current and transconductance of a nonuniformly doped channel MOSFET with ac arbitrary doping profile. Solid State Electron. 38(8):1995;1423-1429.
    • (1995) Solid State Electron , vol.38 , Issue.8 , pp. 1423-1429
    • Wang, C.L.1
  • 10
    • 0029357125 scopus 로고
    • Application of the MOS charge-sheet model to nonuniform doping along the channel
    • Victory J., Sanchez J., DeMassa T., Welfert B. Application of the MOS charge-sheet model to nonuniform doping along the channel. Solid State Electron. 38(8):1995;1497-1503.
    • (1995) Solid State Electron , vol.38 , Issue.8 , pp. 1497-1503
    • Victory, J.1    Sanchez, J.2    DeMassa, T.3    Welfert, B.4
  • 13
    • 0026954176 scopus 로고
    • Source-to-drain nonuniformly doped channel (NUDC) MOSFET structure for high current drivability and threshold voltage controllability
    • Okumura Y., Shirahata M., Hachisuka A., Okudaira T., Arima H., Matsukawa T. Source-to-drain nonuniformly doped channel (NUDC) MOSFET structure for high current drivability and threshold voltage controllability. IEEE Trans. Electron Dev. 39(11):1992;2541-2552.
    • (1992) IEEE Trans. Electron Dev. , vol.39 , Issue.11 , pp. 2541-2552
    • Okumura, Y.1    Shirahata, M.2    Hachisuka, A.3    Okudaira, T.4    Arima, H.5    Matsukawa, T.6
  • 16
    • 0021501347 scopus 로고
    • The effect of high fields on MOS device and circuit performance
    • Sodini C.G., Ko P.K., Moll J.L. The effect of high fields on MOS device and circuit performance. IEEE Trans. Electron Dev. 31:1984;1386-1393.
    • (1984) IEEE Trans. Electron Dev. , vol.31 , pp. 1386-1393
    • Sodini, C.G.1    Ko, P.K.2    Moll, J.L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.