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Volumn 34, Issue 3, 1999, Pages 357-366

CMOS Technology - Year 2010 and Beyond

Author keywords

CMOS; Downsizing; Future; Large scale integrated circuit; Limitation; Technology

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; LSI CIRCUITS; MOSFET DEVICES; TECHNOLOGICAL FORECASTING;

EID: 0033100138     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748187     Document Type: Article
Times cited : (132)

References (25)
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    • Sub-50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions
    • Dec.
    • M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions," in IEDM Tech. Dig., Dec. 1993, pp. 119-122.
    • (1993) IEDM Tech. Dig. , pp. 119-122
    • Ono, M.1    Saito, M.2    Yoshitomi, T.3    Fiegna, C.4    Ohguro, T.5    Iwai, H.6
  • 12
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  • 15
    • 0028448562 scopus 로고
    • Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements
    • _, "Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements," IEEE Trans. Electron Devices, vol. 41, pp. 941-951, 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , pp. 941-951
  • 21
    • 0027889412 scopus 로고
    • 21 psec switching 0.1 μm-CMOS at room temperature using high performance Co salicide process
    • T. Yamazaki, K. Goto, T. Fukano, Y. Nara, T. Sugii, and, T. Ito, "21 psec switching 0.1 μm-CMOS at room temperature using high performance Co salicide process," in IEDM Tech. Dig., 1993, pp. 906-908.
    • (1993) IEDM Tech. Dig. , pp. 906-908
    • Yamazaki, T.1    Goto, K.2    Fukano, T.3    Nara, Y.4    Sugii, T.5    Ito, T.6
  • 22
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    • A 0.05 μm-CMOS with ultra shallow source/drain junctions fabricated by 5keV ion implantation and rapid thermal annealing
    • A. Hori, H. Nakaoka, H. Umimoto, K. Yamashita, M. Takase, H. Shimizu, B. Mizuno, and S. Odanaka, "A 0.05 μm-CMOS with ultra shallow source/drain junctions fabricated by 5keV ion implantation and rapid thermal annealing," in IEDM Tech. Dig., 1994, pp. 485-488.
    • (1994) IEDM Tech. Dig. , pp. 485-488
    • Hori, A.1    Nakaoka, H.2    Umimoto, H.3    Yamashita, K.4    Takase, M.5    Shimizu, H.6    Mizuno, B.7    Odanaka, S.8
  • 25
    • 0029547914 scopus 로고
    • Interconnect scaling - The real limiter to high performance ULSI
    • M. T. Bohr, "Interconnect scaling - The real limiter to high performance ULSI," in IEDM Tech. Dig., 1995, pp. 241-244.
    • (1995) IEDM Tech. Dig. , pp. 241-244
    • Bohr, M.T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.