Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

Solid-State Electronics

Volumn 44, Issue 6, 2000, Pages 917-922

  Pavanello, Marcelo Antonio ^a   Martino, João Antonio ^a   Flandre, Denis ^b  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; IONIZATION OF SOLIDS; SILICON ON INSULATOR TECHNOLOGY;

PARASITIC BIPOLAR EFFECTS;

MOSFET DEVICES;

EID: 0033736623     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00032-0     Document Type: Article

References (21)

1. Chuang C.T., Lu P.F., Anderson C.J. SOI for digital CMOS VLSI: design considerations and advances. Proc IEEE. 86(4):1998;689-720.
2. Yoshimi M, Terauchi M, Murakoshi A, Takahashi M, Matsuzawa K, Shigyo N, Ushiku Y. Technology trends of silicon-on-insulator - its advantages and problems to be solved. IEDM Technical Digest 1994. p. 429-31.
3. Sim J.H., Choi C.H., Kim K. Elimination of parasitic bipolar-induced breakdown effects in ultrathin SOI MOSFETs using narrow-bandgap source (NBS) structure. IEEE Trans Electron Dev. 42(8):1995;1495-1502.
4. Azuma K, Kishi A, Tanigawa M, Kaneko S, Naka T, Ishihama A, Iguchi K, Sakiyama K. Application of Ti salicide process on ultrathin SIMOX wafer. Proceedings of IEEE International SOI Conference 1995. p. 30-1.
5. Horiuchi M, Tamura M. BESS: a source structure that fully suppresses the floating body effects in SOI CMOSFETs. IEDM Technical Digest 1996. p. 121-4.
6. Buti T.N., Ogura S., Rovedo N., Tobimatsu K. A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance. IEEE Trans Electron Dev. 38(8):1991;1757-1764.
7. Shen C.C., Murgia J., Goldsman N., Peckerar M., Melganilis J., Antoniadis D. Use of focused-ion-beam and modeling to optimize submicron MOSFET characteristics. IEEE Trans Electron Dev. 45(2):1998;453-459.
8. Hiroki A, Odanaka S, Hori A. A high performance 0.1 μm MOSFET with asymmetric channel profile. IEDM Technical Digest 1995. p. 439-42.
9. Cheng B, Ramgopal Rao V, Ikegami B, Woo JCS. Realization of 0.1 μm asymmetric channel MOSFET with excellent short-channel performance and reliability. Proceedings of ESSDERC 1998. p. 520-3.
10. Cheng B, Ramgopal Rao V, Woo JCS. Sub-0.18 μm SOI MOSFET using lateral asymmetric channel profile and Ge pre-amorphization salicide technology. Proceedings of IEEE International SOI Conference 1998. p. 113-4.
11. Colinge J.P., Crahay A., DeCeuster D., Dessard V., Gentinne B. Improved LOCOS isolation for thin-film SOI MOSFETs. Electron Lett. 32(19):1996;1834-1835.
12. Pavanello M.A., Martino J.A., Dessard V., Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochem Solid-State Lett. 3(1):2000;50-52.
13. Pavanello MA, Martino JA, Dessard V, Flandre D. The graded-channel SOI MOSFET to alleviate the parasitic bipolar effects and improve the output characteristics. Ninth International Symposium on Silicon-on-Insulator Technology and Devices, 195th Electrochemical Society Meeting, Seattle, USA, 1999. p. 293-8.
14. Flandre D., Ferreira L.F., Jespers P.G.A., Colinge J.P. Modeling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits. Solid-State Electron. 39(4):1996;455-460.
15. TMA TSUPREM-4, version 6.5.0, 1998.
16. TMA MEDICI, version 4.1.0, 1998.
17. Kistler N., Woo J. Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's. IEEE Trans Electron Dev. 41(7):1994;1217-1221.
18. Ver Ploeg E.P., Nguyen C.T., Wong S.S., Plummer J.D. Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's. IEEE Trans Electron Dev. 41(6):1994;970-977.
19. Choi J., Fossum J.G. Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's. IEEE Trans Electron Dev. 38(6):1991;1384-1391.
20. Young K.K., Burns J.A. Avalanche-induced drain-source breakdown in silicon-on-insulator nMOSFETs. IEEE Trans Electron Dev. 35(4):1988;426-431.
21. Veeraraghavan S., Fossum J.G. A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD. IEEE Trans Electron Dev. 35(11):1988;1866-1875.